Description: Four one of the selector FPGA source code, including the module Verilog files and test testbench files
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File list (Check if you may need any files):
MUX41\db\logic_util_heursitic.dat
.....\..\MUX41.cbx.xml
.....\..\MUX41.cmp.rdb
.....\..\MUX41.cmp_merge.kpt
.....\..\MUX41.db_info
.....\..\MUX41.hier_info
.....\..\MUX41.hif
.....\..\MUX41.ipinfo
.....\..\MUX41.lpc.html
.....\..\MUX41.lpc.rdb
.....\..\MUX41.lpc.txt
.....\..\MUX41.map.ammdb
.....\..\MUX41.map.bpm
.....\..\MUX41.map.cdb
.....\..\MUX41.map.hdb
.....\..\MUX41.map.kpt
.....\..\MUX41.map.logdb
.....\..\MUX41.map.qmsg
.....\..\MUX41.map.rdb
.....\..\MUX41.map_bb.cdb
.....\..\MUX41.map_bb.hdb
.....\..\MUX41.map_bb.logdb
.....\..\MUX41.pre_map.hdb
.....\..\MUX41.pti_db_list.ddb
.....\..\MUX41.root_partition.map.reg_db.cdb
.....\..\MUX41.rtlv.hdb
.....\..\MUX41.rtlv_sg.cdb
.....\..\MUX41.rtlv_sg_swap.cdb
.....\..\MUX41.sgdiff.cdb
.....\..\MUX41.sgdiff.hdb
.....\..\MUX41.sld_design_entry.sci
.....\..\MUX41.sld_design_entry_dsc.sci
.....\..\MUX41.smart_action.txt
.....\..\MUX41.tis_db_list.ddb
.....\..\MUX41.tmw_info
.....\..\prev_cmp_MUX41.qmsg
.....\incremental_db\compiled_partitions\MUX41.db_info
.....\..............\...................\MUX41.root_partition.map.cdb
.....\..............\...................\MUX41.root_partition.map.dpi
.....\..............\...................\MUX41.root_partition.map.hbdb.cdb
.....\..............\...................\MUX41.root_partition.map.hbdb.hb_info
.....\..............\...................\MUX41.root_partition.map.hbdb.hdb
.....\..............\...................\MUX41.root_partition.map.hbdb.sig
.....\..............\...................\MUX41.root_partition.map.hdb
.....\..............\...................\MUX41.root_partition.map.kpt
.....\..............\README
.....\MUX41.qpf
.....\MUX41.qsf
.....\MUX41.qws
.....\MUX41.v
.....\MUX41.v.bak
.....\MUX41MUX41.cr.mti
.....\MUX41MUX41.mpf
.....\MUX41_TB.v
.....\MUX41_TB.v.bak
.....\output_files\MUX41.done
.....\............\MUX41.flow.rpt
.....\............\MUX41.map.rpt
.....\............\MUX41.map.summary
.....\vsim.wlf
.....\work\@m@u@x41\verilog.prw
.....\....\........\verilog.psm
.....\....\........\_primary.dat
.....\....\........\_primary.dbs
.....\....\........\_primary.vhd
.....\....\........_@t@b\verilog.prw
.....\....\.............\verilog.psm
.....\....\.............\_primary.dat
.....\....\.............\_primary.dbs
.....\....\.............\_primary.vhd
.....\....\_info
.....\....\_vmake
.....\incremental_db\compiled_partitions
.....\work\@m@u@x41
.....\....\@m@u@x41_@t@b
.....\....\_temp
.....\db
.....\incremental_db
.....\output_files
.....\work
MUX41
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