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Title: vivado_LED_Flow Download
 Description: This project uses verilog HDL to realize the the control of 16 leds loaded on Xilinx Basys3 board.
 Downloaders recently: [More information of uploader 姚罡]
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segV
....\.Xil
....\....\Vivado-11676-DESKTOP-H4J3HD2
....\....\............................\wave
....\segV.cache
....\..........\compile_simlib
....\..........\wt
....\..........\..\java_command_handlers.wdf
....\..........\..\synthesis.wdf
....\..........\..\synthesis_details.wdf
....\..........\..\webtalk_pa.xml
....\..........\..\xsim.wdf
....\segV.hw
....\.......\hw_1
....\.......\....\hw.xml
....\.......\....\wave
....\segV.runs
....\.........\.jobs
....\.........\.....\vrs_config_1.xml
....\.........\.....\vrs_config_10.xml
....\.........\.....\vrs_config_11.xml
....\.........\.....\vrs_config_12.xml
....\.........\.....\vrs_config_13.xml
....\.........\.....\vrs_config_14.xml
....\.........\.....\vrs_config_15.xml
....\.........\.....\vrs_config_16.xml
....\.........\.....\vrs_config_17.xml
....\.........\.....\vrs_config_18.xml
....\.........\.....\vrs_config_19.xml
....\.........\.....\vrs_config_2.xml
....\.........\.....\vrs_config_20.xml
....\.........\.....\vrs_config_21.xml
....\.........\.....\vrs_config_22.xml
....\.........\.....\vrs_config_3.xml
....\.........\.....\vrs_config_4.xml
....\.........\.....\vrs_config_5.xml
....\.........\.....\vrs_config_6.xml
....\.........\.....\vrs_config_7.xml
....\.........\.....\vrs_config_8.xml
....\.........\.....\vrs_config_9.xml
....\.........\impl_1
....\.........\......\.init_design.begin.rst
....\.........\......\.init_design.end.rst
....\.........\......\.opt_design.begin.rst
....\.........\......\.opt_design.end.rst
....\.........\......\.place_design.begin.rst
....\.........\......\.place_design.end.rst
....\.........\......\.route_design.begin.rst
....\.........\......\.route_design.end.rst
....\.........\......\.vivado.begin.rst
....\.........\......\.vivado.end.rst
....\.........\......\.Vivado_Implementation.queue.rst
....\.........\......\.write_bitstream.begin.rst
....\.........\......\.write_bitstream.end.rst
....\.........\......\.Xil
....\.........\......\gen_run.xml
....\.........\......\htr.txt
....\.........\......\init_design.pb
....\.........\......\ISEWrap.js
....\.........\......\ISEWrap.sh
....\.........\......\opt_design.pb
....\.........\......\place_design.pb
....\.........\......\project.wdf
....\.........\......\route_design.pb
....\.........\......\rundef.js
....\.........\......\runme.bat
....\.........\......\runme.log
....\.........\......\runme.sh
....\.........\......\segFlow.bin
....\.........\......\segFlow.bit
....\.........\......\segFlow.tcl
....\.........\......\segFlow.vdi
....\.........\......\segFlow_10168.backup.vdi
....\.........\......\segFlow_10404.backup.vdi
....\.........\......\segFlow_5444.backup.vdi
....\.........\......\segFlow_9224.backup.vdi
....\.........\......\segFlow_clock_utilization_placed.rpt
....\.........\......\segFlow_control_sets_placed.rpt
....\.........\......\segFlow_drc_opted.rpt
....\.........\......\segFlow_drc_routed.pb
....\.........\......\segFlow_drc_routed.rpt
....\.........\......\segFlow_io_placed.rpt
....\.........\......\segFlow_opt.dcp
....\.........\......\segFlow_placed.dcp
....\.........\......\segFlow_power_routed.rpt
....\.........\......\segFlow_power_summary_routed.pb
....\.........\......\segFlow_routed.dcp
....\.........\......\segFlow_route_status.pb
....\.........\......\segFlow_route_status.rpt
....\.........\......\segFlow_timing_summary_routed.rpt
....\.........\......\segFlow_timing_summary_routed.rpx
....\.........\......\segFlow_utilization_placed.pb
....\.........\......\segFlow_utilization_placed.rpt
....\.........\......\usage_statistics_webtalk.html
....\.........\......\usage_statistics_webtalk.xml
....\.........\......\vivado.jou
....\.........\......\vivado.pb
....\.........\......\vivado_10168.backup.jou
....\.........\......\vivado_10404.backup.jou
....\.........\......\vivado_5444.backup.jou
    

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