VGA_CPLD
........\Com.v
........\Com.v.bak
........\db
........\..\logic_util_heursitic.dat
........\..\prev_cmp_VGA_CPLD.asm.qmsg
........\..\prev_cmp_VGA_CPLD.eda.qmsg
........\..\prev_cmp_VGA_CPLD.fit.qmsg
........\..\prev_cmp_VGA_CPLD.map.qmsg
........\..\prev_cmp_VGA_CPLD.qmsg
........\..\prev_cmp_VGA_CPLD.tan.qmsg
........\..\VGA_CPLD.asm.qmsg
........\..\VGA_CPLD.asm_labs.ddb
........\..\VGA_CPLD.cbx.xml
........\..\VGA_CPLD.cmp.cdb
........\..\VGA_CPLD.cmp.hdb
........\..\VGA_CPLD.cmp.kpt
........\..\VGA_CPLD.cmp.logdb
........\..\VGA_CPLD.cmp.rdb
........\..\VGA_CPLD.cmp.tdb
........\..\VGA_CPLD.cmp0.ddb
........\..\VGA_CPLD.db_info
........\..\VGA_CPLD.eco.cdb
........\..\VGA_CPLD.eda.qmsg
........\..\VGA_CPLD.fit.qmsg
........\..\VGA_CPLD.hier_info
........\..\VGA_CPLD.hif
........\..\VGA_CPLD.lpc.html
........\..\VGA_CPLD.lpc.rdb
........\..\VGA_CPLD.lpc.txt
........\..\VGA_CPLD.map.cdb
........\..\VGA_CPLD.map.hdb
........\..\VGA_CPLD.map.logdb
........\..\VGA_CPLD.map.qmsg
........\..\VGA_CPLD.pre_map.cdb
........\..\VGA_CPLD.pre_map.hdb
........\..\VGA_CPLD.rtlv.hdb
........\..\VGA_CPLD.rtlv_sg.cdb
........\..\VGA_CPLD.rtlv_sg_swap.cdb
........\..\VGA_CPLD.sgdiff.cdb
........\..\VGA_CPLD.sgdiff.hdb
........\..\VGA_CPLD.sld_design_entry.sci
........\..\VGA_CPLD.sld_design_entry_dsc.sci
........\..\VGA_CPLD.syn_hier_info
........\..\VGA_CPLD.tan.qmsg
........\..\VGA_CPLD.tis_db_list.ddb
........\..\VGA_CPLD.tmw_info
........\..\VGA_CPLD_global_asgn_op.abo
........\HV_crtl.v
........\hv_crtl.v.bak
........\HV_ctrl.v.bak
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\VGA_CPLD.db_info
........\..............\...................\VGA_CPLD.root_partition.map.kpt
........\..............\README
........\output_files
........\............\stp1.stp
........\............\VGA_CPLD.asm.rpt
........\............\VGA_CPLD.cdf
........\............\VGA_CPLD.done
........\............\VGA_CPLD.eda.rpt
........\............\VGA_CPLD.fit.rpt
........\............\VGA_CPLD.fit.smsg
........\............\VGA_CPLD.fit.summary
........\............\VGA_CPLD.flow.rpt
........\............\VGA_CPLD.jdi
........\............\VGA_CPLD.map.rpt
........\............\VGA_CPLD.map.smsg
........\............\VGA_CPLD.map.summary
........\............\VGA_CPLD.pin
........\............\VGA_CPLD.pof
........\............\VGA_CPLD.sta.rpt
........\............\VGA_CPLD.sta.summary
........\............\VGA_CPLD.tan.rpt
........\............\VGA_CPLD.tan.summary
........\simulation
........\..........\modelsim
........\..........\........\modelsim.ini
........\..........\........\msim_transcript
........\..........\........\rtl_work
........\..........\........\........\com
........\..........\........\........\...\verilog.prw
........\..........\........\........\...\verilog.psm
........\..........\........\........\...\_primary.dat
........\..........\........\........\...\_primary.dbs
........\..........\........\........\...\_primary.vhd
........\..........\........\........\_info
........\..........\........\........\_temp
........\..........\........\........\.....\vlogb0i0ga
........\..........\........\........\_vmake
........\..........\........\VGA_CPLD.sft
........\..........\........\VGA_CPLD.vo
........\..........\........\VGA_CPLD.vt
........\..........\........\VGA_CPLD.vt.bak
........\..........\........\VGA_CPLD_modelsim.xrf
........\..........\........\VGA_CPLD_run_msim_rtl_verilog.do
........\..........\........\VGA_CPLD_run_msim_rtl_verilog.do.bak
........\..........\........\VGA_CPLD_run_msim_rtl_verilog.do.bak1
........\..........\........\VGA_CPLD_run_msim_rtl_verilog.do.bak10