- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 27kb
- Update:
- 2016-05-27
- Downloads:
- 0 Times
- Uploaded by:
- 张琼
Description: VHDL to achieve traffic lights, through the frequency control and the frequency of the lamp control and delay, the use of a variety of frequency control clock to control the process.
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example7_jtd\db\jtd.db_info
............\..\jtd.eco.cdb
............\..\jtd.sld_design_entry.sci
............\jtd.asm.rpt
............\jtd.cdf
............\jtd.done
............\jtd.dpf
............\jtd.fit.rpt
............\jtd.fit.smsg
............\jtd.fit.summary
............\jtd.flow.rpt
............\jtd.map.rpt
............\jtd.map.summary
............\jtd.pin
............\jtd.pof
............\jtd.qpf
............\jtd.qsf
............\jtd.qws
............\jtd.tan.rpt
............\jtd.tan.summary
............\jtd.vhd
............\db
example7_jtd
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