Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: example3_counter_add_up Download
 Description: VHDL language implementation of the digital display and control of the button, in the control of the button can be achieved even add, even the function of the display.
 Downloaders recently: [More information of uploader 张琼]
 To Search:
File list (Check if you may need any files):
 

example3_counter_add_up\counter.asm.rpt
.......................\counter.bsf
.......................\counter.cdf
.......................\counter.done
.......................\counter.dpf
.......................\counter.fit.rpt
.......................\counter.fit.smsg
.......................\counter.fit.summary
.......................\counter.flow.rpt
.......................\counter.map.rpt
.......................\counter.map.summary
.......................\counter.pin
.......................\counter.pof
.......................\counter.qpf
.......................\counter.qsf
.......................\counter.qws
.......................\counter.tan.rpt
.......................\counter.tan.summary
.......................\counter.vhd
.......................\counter_assignment_defaults.qdf
.......................\db\counter.db_info
.......................\..\counter.eco.cdb
.......................\..\counter.map.qmsg
.......................\..\counter.sld_design_entry.sci
.......................\实验说明.txt
.......................\db
example3_counter_add_up
    

CodeBus www.codebus.net