Description: Own use Verilog write serial reception procedures, testbench, can achieve single-byte receive and continuous reception, testbench measurable function
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File list (Check if you may need any files):
rtl\uart_byte_tx.v
...\UART_RX.v
...\UART_RX.v.bak
...\UART_RX_tb.v
...\UART_RX_top.v
...\UART_RX_top.v.bak
rtl
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