Description: Design of Electronic Clock Based on Onboard DS1302
AX301 development board is equipped with a real-time clock (RTC) chip, model DS1302. Learn and master the basic principles of DS1302, and complete the design of electronic clock.
Requirements: (1) with a digital display, minutes, seconds
(2) has the time preset function
To Search:
File list (Check if you may need any files):
DS1302\chuchan.v
......\clk200Hz.v
......\clk500k.v
......\display.v
......\DS1302.asm.rpt
......\DS1302.done
......\DS1302.fit.rpt
......\DS1302.fit.smsg
......\DS1302.fit.summary
......\DS1302.flow.rpt
......\DS1302.map.rpt
......\DS1302.map.summary
......\DS1302.pin
......\DS1302.qpf
......\DS1302.qsf
......\DS1302.sof
......\DS1302.sta.rpt
......\DS1302.sta.summary
......\DS1302.v
......\DS1302_ctrl.v
......\flash_gen.v
......\HEX.v
......\SHEX.v
......\time_set.v
......\db\DS1302.amm.cdb
......\..\DS1302.asm.qmsg
......\..\DS1302.asm.rdb
......\..\DS1302.asm_labs.ddb
......\..\DS1302.cbx.xml
......\..\DS1302.cmp.bpm
......\..\DS1302.cmp.cdb
......\..\DS1302.cmp.hdb
......\..\DS1302.cmp.kpt
......\..\DS1302.cmp.logdb
......\..\DS1302.cmp.rdb
......\..\DS1302.cmp_merge.kpt
......\..\DS1302.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
......\..\DS1302.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
......\..\DS1302.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
......\..\DS1302.db_info
......\..\DS1302.fit.qmsg
......\..\DS1302.hier_info
......\..\DS1302.hif
......\..\DS1302.idb.cdb
......\..\DS1302.lpc.html
......\..\DS1302.lpc.rdb
......\..\DS1302.lpc.txt
......\..\DS1302.map.bpm
......\..\DS1302.map.cdb
......\..\DS1302.map.hdb
......\..\DS1302.map.kpt
......\..\DS1302.map.logdb
......\..\DS1302.map.qmsg
......\..\DS1302.map_bb.cdb
......\..\DS1302.map_bb.hdb
......\..\DS1302.map_bb.logdb
......\..\DS1302.pre_map.cdb
......\..\DS1302.pre_map.hdb
......\..\DS1302.rtlv.hdb
......\..\DS1302.rtlv_sg.cdb
......\..\DS1302.rtlv_sg_swap.cdb
......\..\DS1302.sgdiff.cdb
......\..\DS1302.sgdiff.hdb
......\..\DS1302.sld_design_entry.sci
......\..\DS1302.sld_design_entry_dsc.sci
......\..\DS1302.smart_action.txt
......\..\DS1302.smp_dump.txt
......\..\DS1302.sta.qmsg
......\..\DS1302.sta.rdb
......\..\DS1302.sta_cmp.8_slow_1200mv_85c.tdb
......\..\DS1302.syn_hier_info
......\..\DS1302.tiscmp.fastest_slow_1200mv_0c.ddb
......\..\DS1302.tiscmp.fastest_slow_1200mv_85c.ddb
......\..\DS1302.tiscmp.fast_1200mv_0c.ddb
......\..\DS1302.tiscmp.slow_1200mv_0c.ddb
......\..\DS1302.tiscmp.slow_1200mv_85c.ddb
......\..\DS1302.tis_db_list.ddb
......\..\DS1302.tmw_info
......\..\logic_util_heursitic.dat
......\..\prev_cmp_DS1302.qmsg
......\..\altsyncram_eu14.tdf
......\..\altsyncram_ku14.tdf
......\..\cmpr_ngc.tdf
......\..\cmpr_qgc.tdf
......\..\cmpr_rgc.tdf
......\..\cntr_23j.tdf
......\..\cntr_egi.tdf
......\..\cntr_fgi.tdf
......\..\cntr_i6j.tdf
......\..\cntr_jgi.tdf
......\..\decode_dvf.tdf
......\..\DS1302.autoh_e40e1.map.reg_db.cdb
......\..\DS1302.autos_3e921.map.reg_db.cdb
......\..\DS1302.cmp.idb
......\..\DS1302.ipinfo
......\..\DS1302.map.ammdb
......\..\DS1302.map.rdb
......\..\DS1302.pplq.rdb
......\..\DS1302.pti_db_list.ddb
......\..\DS1302.root_partition.map.reg_db.cdb
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