- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 33kb
- Update:
- 2017-02-14
- Downloads:
- 0 Times
- Uploaded by:
- 邢晶玉
Description: Through a simple and complete and typical 12-band counter VHDL design examples, to make preliminary understanding of VHDL expression and the resulting VHDL language phenomenon and statement rules. So that we can quickly grasp the overall VHDL program the basic structure and design features to achieve the purpose of quick start.
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CNT12
.....\COUNT12EN.sym
.....\LIB.DLS
.....\U2877566.DLS
.....\U6333996.DLS
.....\U6730148.DLS
.....\count12en.acf
.....\count12en.fit
.....\count12en.hex
.....\count12en.hif
.....\count12en.mmf
.....\count12en.ndb
.....\count12en.pin
.....\count12en.pof
.....\count12en.rpt
.....\count12en.scf
.....\count12en.snf
.....\count12en.sof
.....\count12en.ttf
.....\count12en.vhd
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