第二章\add_share.v
......\add_share1.v
......\add_test.v
......\ahb2sram.v
......\basic_shift_register.v
......\clock.v
......\CM1RegFile.v
......\dpram_fpga.v
......\DSPuva16.v
......\DW02_mac_async.v
......\fifo_asynch.v
......\gray.v
......\LUT_2bit_inc.v
......\lvds.v
......\modelsim_sim.tcl
......\multi_seq_full.v
......\PowerN_comb2.v
......\quartus_ddc.tcl
......\quartus_ddc.tcl.bak
......\ram.c
......\ram_reset_mux.v
......\reg_reset.v
......\reset_cnt.v
......\reset_sync.v
......\rom.v
......\SIMDAdder.v
......\single_port_rom.v
......\smbus_slave_ram_top.v
......\spram.v
......\SPRAM_ASIC.v
......\sram_fir.cpp
......\sram_fpga.v
......\state_trigger.c
......\synthesis.v
......\syn_fifo.v
......\TimesN_comb1.v
......\TimesN_pipe.v
......\true_dpram.v
......\un_synthsis.v
......\usb_blaster_vjtag.tcl
......\vjtag_connect.py
......\vjtag_if_best.v
......\vJTAG_interface.v
......\vJTAG_interface_word.v
第二章