lab_3\.DS_Store
lab_3\05a_Multicycle.pdf
lab_3\05_Nonpipelined.pdf
lab_3\ALU.v
lab_3\alustim.v
lab_3\datamem.v
lab_3\Datapath.v
lab_3\Datapath.v.zip
lab_3\instrmem.v
lab_3\instrmem.v.bak
lab_3\instructionFecth.v
lab_3\instructionFecth.v.bak
lab_3\instructionFetch.cr.mti
lab_3\instructionFetch.mpf
lab_3\instruction_fetch-mau.v
lab_3\lab3.doc
lab_3\regstim.v
lab_3\THUVIEN.v
lab_3\vsim.wlf
lab_3\binary\test01.out
lab_3\binary\test02.out
lab_3\binary\test03.out
lab_3\binary\test04.out
lab_3\binary\test05.out
lab_3\binary\test06.out
lab_3\binary\test07.out
lab_3\binary\test08.out
lab_3\binary\test09.out
lab_3\side-by-side\test01_AddiJ.txt
lab_3\side-by-side\test02_subu.txt
lab_3\side-by-side\test03_nor.txt
lab_3\side-by-side\test04_J_Jr.txt
lab_3\side-by-side\test05_LwSw.txt
lab_3\side-by-side\test06_bltz.txt
lab_3\side-by-side\test07_sltu.txt
lab_3\side-by-side\test08_Forwarding.txt
lab_3\side-by-side\test09_Sorter.txt
lab_3\source\test01_AddiJ.txt
lab_3\source\test02_subu.txt
lab_3\source\test03_nor.txt
lab_3\source\test04_J_Jr.txt
lab_3\source\test05_LwSw.txt
lab_3\source\test06_bltz.txt
lab_3\source\test07_sltu.txt
lab_3\source\test08_Forwarding.txt
lab_3\source\test09_Sorter.txt
lab_3\work\_info
lab_3\work\_vmake
lab_3\work\@instruction@mem\verilog.asm
lab_3\work\@instruction@mem\verilog.rw
lab_3\work\@instruction@mem\_primary.dat
lab_3\work\@instruction@mem\_primary.dbs
lab_3\work\@instruction@mem\_primary.vhd
lab_3\work\@instructionfetch\verilog.asm
lab_3\work\@instructionfetch\verilog.rw
lab_3\work\@instructionfetch\_primary.dat
lab_3\work\@instructionfetch\_primary.dbs
lab_3\work\@instructionfetch\_primary.vhd
lab_3\work\@mux2to1\verilog.asm
lab_3\work\@mux2to1\verilog.rw
lab_3\work\@mux2to1\_primary.dat
lab_3\work\@mux2to1\_primary.dbs
lab_3\work\@mux2to1\_primary.vhd
lab_3\work\@mux4to1\verilog.asm
lab_3\work\@mux4to1\verilog.rw
lab_3\work\@mux4to1\_primary.dat
lab_3\work\@mux4to1\_primary.dbs
lab_3\work\@mux4to1\_primary.vhd
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