Description: The bus system is based on FPGA chip. It adds digital tube display module, voice automatic reporting module and infrared communication module. The bus stop system adopts FPGA as the core of the main control chip, add LCD module, infrared communication module, RS232 bus module, indicator light display module and so on.
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File list (Check if you may need any files):
bus_top
bus_top\bus_top.asm.rpt
bus_top\bus_top.cdf
bus_top\bus_top.done
bus_top\bus_top.fit.rpt
bus_top\bus_top.fit.smsg
bus_top\bus_top.fit.summary
bus_top\bus_top.flow.rpt
bus_top\bus_top.jdi
bus_top\bus_top.map.rpt
bus_top\bus_top.map.smsg
bus_top\bus_top.map.summary
bus_top\bus_top.pin
bus_top\bus_top.qpf
bus_top\bus_top.qsf
bus_top\bus_top.qws
bus_top\bus_top.sof
bus_top\bus_top.sta.rpt
bus_top\bus_top.sta.summary
bus_top\bus_top.v
bus_top\bus_top.v.bak
bus_top\db
bus_top\db\bus_top.amm.cdb
bus_top\db\bus_top.asm.qmsg
bus_top\db\bus_top.asm.rdb
bus_top\db\bus_top.cbx.xml
bus_top\db\bus_top.cmp.kpt
bus_top\db\bus_top.cmp.rdb
bus_top\db\bus_top.cmp_merge.kpt
bus_top\db\bus_top.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
bus_top\db\bus_top.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
bus_top\db\bus_top.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
bus_top\db\bus_top.db_info
bus_top\db\bus_top.fit.qmsg
bus_top\db\bus_top.hier_info
bus_top\db\bus_top.hif
bus_top\db\bus_top.idb.cdb
bus_top\db\bus_top.lpc.html
bus_top\db\bus_top.lpc.rdb
bus_top\db\bus_top.lpc.txt
bus_top\db\bus_top.map.bpm
bus_top\db\bus_top.map.cdb
bus_top\db\bus_top.map.hdb
bus_top\db\bus_top.map.kpt
bus_top\db\bus_top.map.logdb
bus_top\db\bus_top.map.qmsg
bus_top\db\bus_top.map.rdb
bus_top\db\bus_top.map_bb.cdb
bus_top\db\bus_top.map_bb.hdb
bus_top\db\bus_top.map_bb.logdb
bus_top\db\bus_top.pre_map.cdb
bus_top\db\bus_top.pre_map.hdb
bus_top\db\bus_top.root_partition.map.reg_db.cdb
bus_top\db\bus_top.routing.rdb
bus_top\db\bus_top.rtlv.hdb
bus_top\db\bus_top.rtlv_sg.cdb
bus_top\db\bus_top.rtlv_sg_swap.cdb
bus_top\db\bus_top.sgdiff.cdb
bus_top\db\bus_top.sgdiff.hdb
bus_top\db\bus_top.sld_design_entry.sci
bus_top\db\bus_top.sld_design_entry_dsc.sci
bus_top\db\bus_top.smart_action.txt
bus_top\db\bus_top.sta.qmsg
bus_top\db\bus_top.sta.rdb
bus_top\db\bus_top.syn_hier_info
bus_top\db\bus_top.tiscmp.fastest_slow_1200mv_0c.ddb
bus_top\db\bus_top.tiscmp.fastest_slow_1200mv_85c.ddb
bus_top\db\bus_top.tiscmp.fast_1200mv_0c.ddb
bus_top\db\bus_top.tiscmp.slow_1200mv_0c.ddb
bus_top\db\bus_top.tiscmp.slow_1200mv_85c.ddb
bus_top\db\bus_top.tis_db_list.ddb
bus_top\db\bus_top.tmw_info
bus_top\db\logic_util_heursitic.dat
bus_top\db\prev_cmp_bus_top.qmsg
bus_top\HWBZ.v
bus_top\HW_SB.v
bus_top\incremental_db
bus_top\incremental_db\compiled_partitions
bus_top\incremental_db\compiled_partitions\bus_top.db_info
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.cmp.cdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.cmp.dfp
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.cmp.hdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.cmp.kpt
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.cmp.logdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.cmp.rcfdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.cdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.dpi
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.hbdb.cdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.hbdb.hb_info
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.hbdb.hdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.hbdb.sig
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.hdb
bus_top\incremental_db\compiled_partitions\bus_top.root_partition.map.kpt
bus_top\incremental_db\README
bus_top\jq.v
bus_top\jq.v.bak
bus_top\lcd.v
bus_top\lcd.v.bak
bus_top\motor1.v
bus_top\nec_rx.v
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