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Title: 实验1 Download
 Description: Achieve decoder with verilog language, including experimental data stream file
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extend.v
logic_gates_1.bit
logic_gates_1.v
logic_gates_2.bit
logic_gates_2.v
logic_gates_3.bit
logic_gates_3.v
logic_gates_tb.v
logisim原理图.circ
three_state_gates.bit
three_state_gates.v

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