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Title: dds6_ise12migration Download
 Description: With DE2 as the development platform and Veriolg language programming, the DDS signal output, frequency, step and waveform output can be adjusted. The correctness of the design is verified by using Modelsim and FPGA embedded logic analyzer, which can meet certain engineering requirements
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File list (Check if you may need any files):
FilenameSizeDate
.lso 6 2009-11-23
blk_mem_gen_ds512.pdf 1333109 2009-10-24
blk_mem_gen_release_notes.txt 6020 2009-10-24
dds.cmd_log 372 2009-11-23
dds.lso 6 2009-10-24
dds.ngc 41954 2009-11-23
dds.ngr 19862 2009-11-23
dds.prj 22 2009-11-23
dds.stx 903 2009-11-23
dds.syr 17724 2009-11-23
dds.v 1870 2009-11-23
dds.xst 1110 2009-11-23
dds6.ise 280243 2017-11-20
dds6.ise_ISE_Backup 280048 2009-12-10
dds6.ntrc_log 220 2009-11-23
dds6_xdb
dds6_xdb\tmp
dds_summary.html 3566 2009-12-10
dds_vhdl.prj 80 2009-10-24
isim
isim\temp
isim\temp\hdllib.ref 327 2009-11-16
isim\temp\hdpdeps.ref 664 2009-11-16
isim\temp\vlg03
isim\temp\vlg03\test__dds__v.bin 2244 2009-11-16
isim\temp\vlg2B
isim\temp\vlg2B\dds.bin 5802 2009-11-16
isim\temp\vlg2D
isim\temp\vlg2D\glbl.bin 3401 2009-11-16
isim\temp\vlg43
isim\temp\vlg43\rom__cose.bin 4415 2009-11-16
isim\temp\vlg64
isim\temp\vlg64\rom__sine.bin 4415 2009-11-16
isim\work
isim\work\dds
isim\work\dds\dds.h 915 2009-11-16
isim\work\dds\mingw
isim\work\dds\mingw\dds.obj 34704 2009-11-16
isim\work\glbl
isim\work\glbl\glbl.h 946 2009-11-16
isim\work\glbl\mingw
isim\work\glbl\mingw\glbl.obj 25182 2009-11-16
isim\work\hdllib.ref 327 2009-11-16
isim\work\hdpdeps.ref 639 2009-11-16
isim\work\rom__cose
isim\work\rom__cose\mingw
isim\work\rom__cose\mingw\rom__cose.obj 13958 2009-11-16
isim\work\rom__cose\rom__cose.h 948 2009-11-16
isim\work\rom__sine
isim\work\rom__sine\mingw
isim\work\rom__sine\mingw\rom__sine.obj 13958 2009-11-16
isim\work\rom__sine\rom__sine.h 948 2009-11-16
isim\work\test__dds__v
isim\work\test__dds__v\mingw
isim\work\test__dds__v\mingw\test__dds__v.obj 21575 2009-11-16
isim\work\test__dds__v\test__dds__v.h 959 2009-11-16
isim\work\test__dds__v\xsimtest__dds__v.cpp 4763 2009-11-16
isim\work\vlg03
isim\work\vlg03\test__dds__v.bin 2244 2009-11-16
isim\work\vlg2B
isim\work\vlg2B\dds.bin 5802 2009-11-16
isim\work\vlg2D
isim\work\vlg2D\glbl.bin 3401 2009-11-16
isim\work\vlg43
isim\work\vlg43\rom__cose.bin 4415 2009-11-16
isim\work\vlg64
isim\work\vlg64\rom__sine.bin 4415 2009-11-16
isim\xilinxcorelib_ver.auxlib
isim\xilinxcorelib_ver.auxlib\hdllib.ref 235 2009-11-16
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1\mingw
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1\mingw\_b_l_k___m_e_m___g_e_n___v2__1.obj 433615 2009-11-16
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1\_b_l_k___m_e_m___g_e_n___v2__1.h 9512 2009-11-16
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1__output__stage
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1__output__stage\mingw
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1__output__stage\mingw\_b_l_k___m_e_m___g_e_n___v2__1__output__stage.obj 85051 2009-11-16
isim\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__1__output__stage\_b_l_k___m_e_m___g_e_n___v2__1__output__stage.h 2855 2009-11-16
isim.cmd 14 2009-11-16
isim.hdlsourcefiles 78 2009-11-16
isim.log 4038 2009-11-16
isim.tmp_save
isim.tmp_save\_1 39720 2009-11-16
isimwavedata.xwv 23592 2009-11-16
rom_cos.coe 8668 2009-10-24
rom_cose.asy 349 2009-10-24
rom_cose.mif 18432 2009-10-24
rom_cose.ngc 17566 2009-10-24
rom_cose.sym 645 2009-10-24
rom_cose.v 4314 2009-10-24
rom_cose.veo 3005 2009-10-24
rom_cose.vhd 4669 2009-10-24
rom_cose.vho 3422 2009-10-24
rom_cose.xco 2042 2009-10-24
rom_cose_flist.txt 202 2009-10-24
rom_cose_readme.txt 1941 2009-10-24
rom_cose_xmdf.tcl 3181 2009-10-24
rom_sin.coe 9282 2009-10-28
rom_sine.asy 349 2009-10-24
rom_sine.mif 18432 2009-10-24
rom_sine.ngc 17566 2009-10-24

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