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Title: ethernet_loopback Download
 Description: Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation
 Downloaders recently: [More information of uploader 刘伟杰 ]
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FilenameSizeDate
20171017.cfi 480 2017-10-17
20171017.mcs 4084021 2017-10-17
20171017.prm 712 2017-10-17
checksum.fdo 1317 2015-11-21
checksum.udo 381 2015-11-21
checksum_summary.html 3898 2015-09-16
checksum_wave.fdo 426 2015-11-21
crc_envsettings.html 10185 2015-09-16
crc_summary.html 3997 2015-09-16
ethernet_loopback.cfi 489 2015-11-20
ethernet_loopback.mcs 4084021 2015-11-20
ethernet_loopback.prm 730 2015-11-20
ethernet_send.cfi 460 2015-08-18
ethernet_send.gise 20193 2017-10-17
ethernet_send.prm 672 2015-08-18
ethernet_send.xise 40671 2017-10-17
header_ram.coe 314 2015-11-20
ipcore_dir
ipcore_dir\coregen.cgp 238 2015-11-09
ipcore_dir\coregen.log 2977 2017-10-17
ipcore_dir\create_e_mac.tcl 1284 2015-11-19
ipcore_dir\create_fifo_48_48_64.tcl 1274 2015-08-27
ipcore_dir\create_fifo_64_8_1024.tcl 1275 2015-08-19
ipcore_dir\create_fifo_8_8_2048.tcl 1274 2015-08-21
ipcore_dir\create_ram_16x32.tcl 1280 2015-11-09
ipcore_dir\create_ram_8x50.tcl 1279 2015-11-09
ipcore_dir\edit_fifo_64_8_1024.tcl 1130 2015-08-21
ipcore_dir\edit_fifo_8_8_2048.tcl 1129 2015-09-16
ipcore_dir\edit_ram_8x50.tcl 1124 2017-10-17
ipcore_dir\fifo_48_48_64
ipcore_dir\fifo_48_48_64.asy 889 2015-08-27
ipcore_dir\fifo_48_48_64.gise 1384 2017-10-17
ipcore_dir\fifo_48_48_64.ncf
ipcore_dir\fifo_48_48_64.ngc 75898 2015-08-27
ipcore_dir\fifo_48_48_64.sym 2437 2015-08-27
ipcore_dir\fifo_48_48_64.v 14194 2015-08-27
ipcore_dir\fifo_48_48_64.veo 4561 2015-08-27
ipcore_dir\fifo_48_48_64.xco 7309 2015-08-27
ipcore_dir\fifo_48_48_64.xise 4933 2015-08-28
ipcore_dir\fifo_48_48_64\doc
ipcore_dir\fifo_48_48_64\doc\fifo_generator_v9_3_readme.txt 9862 2015-08-27
ipcore_dir\fifo_48_48_64\doc\fifo_generator_v9_3_vinfo.html 10447 2015-08-27
ipcore_dir\fifo_48_48_64\doc\pg057-fifo-generator.pdf 75348 2015-08-27
ipcore_dir\fifo_48_48_64\example_design
ipcore_dir\fifo_48_48_64\example_design\fifo_48_48_64_exdes.ucf 2781 2015-08-27
ipcore_dir\fifo_48_48_64\example_design\fifo_48_48_64_exdes.vhd 5243 2015-08-27
ipcore_dir\fifo_48_48_64\fifo_generator_v9_3_readme.txt 9862 2013-10-14
ipcore_dir\fifo_48_48_64\implement
ipcore_dir\fifo_48_48_64\implement\implement.bat 3372 2015-08-27
ipcore_dir\fifo_48_48_64\implement\implement.sh 3280 2015-08-27
ipcore_dir\fifo_48_48_64\implement\implement_synplify.bat 3383 2015-08-27
ipcore_dir\fifo_48_48_64\implement\implement_synplify.sh 3293 2015-08-27
ipcore_dir\fifo_48_48_64\implement\planAhead_ise.bat 2634 2015-08-27
ipcore_dir\fifo_48_48_64\implement\planAhead_ise.sh 2585 2015-08-27
ipcore_dir\fifo_48_48_64\implement\planAhead_ise.tcl 3188 2015-08-27
ipcore_dir\fifo_48_48_64\implement\xst.prj 48 2015-08-27
ipcore_dir\fifo_48_48_64\implement\xst.scr 236 2015-08-27
ipcore_dir\fifo_48_48_64\simulation
ipcore_dir\fifo_48_48_64\simulation\fifo_48_48_64_dgen.vhd 4674 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\fifo_48_48_64_dverif.vhd 6002 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\fifo_48_48_64_pctrl.vhd 18848 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\fifo_48_48_64_pkg.vhd 11755 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\fifo_48_48_64_rng.vhd 4002 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\fifo_48_48_64_synth.vhd 11306 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\fifo_48_48_64_tb.vhd 6309 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional
ipcore_dir\fifo_48_48_64\simulation\functional\simulate_isim.bat 3016 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\simulate_isim.sh 3047 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\simulate_mti.bat 2294 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\simulate_mti.do 3118 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\simulate_mti.sh 2343 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\simulate_ncsim.bat 3101 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\simulate_vcs.bat 3001 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\ucli_commands.key 80 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\vcs_session.tcl 3827 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\wave_isim.tcl 3197 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\wave_mti.do 4146 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\functional\wave_ncsim.sv 3478 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing
ipcore_dir\fifo_48_48_64\simulation\timing\simulate_isim.bat 2995 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\simulate_isim.sh 3027 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\simulate_mti.bat 2294 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\simulate_mti.do 3124 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\simulate_mti.sh 2343 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\simulate_ncsim.bat 3316 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\simulate_vcs.bat 3028 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\ucli_commands.key 80 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\vcs_session.tcl 3825 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\wave_isim.tcl 3197 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\wave_mti.do 4146 2015-08-27
ipcore_dir\fifo_48_48_64\simulation\timing\wave_ncsim.sv 3478 2015-08-27
ipcore_dir\fifo_48_48_64_flist.txt 2504 2015-08-27
ipcore_dir\fifo_48_48_64_xmdf.tcl 11877 2015-08-27
ipcore_dir\fifo_64_8_1024
ipcore_dir\fifo_64_8_1024.asy 1080 2015-08-19
ipcore_dir\fifo_64_8_1024.gise 1388 2015-09-16
ipcore_dir\fifo_64_8_1024.ncf
ipcore_dir\fifo_64_8_1024.ngc 171702 2015-08-19
ipcore_dir\fifo_64_8_1024.sym 2919 2015-08-19
ipcore_dir\fifo_64_8_1024.v 14306 2015-08-19

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