- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 61kb
- Update:
- 2017-11-29
- Downloads:
- 0 Times
- Uploaded by:
- 鞠春鸽
Description: The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustment step 0.1%.
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| PWM\lr_PWM.png | 4747 | 2017-11-03
|
| PWM\lr_PWM.v | 2406 | 2017-11-03
|
| PWM\lr_PWM_1.png | 9631 | 2017-11-03
|
| PWM\lr_PWM_tb.v | 982 | 2017-11-03
|
| PWM\实现内容.txt | 358 | 2017-11-29
|
| PWM\接口逻辑图.jpg | 49080 | 2017-11-03
|
| PWM |
Download