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Title: vga_7_0728 Download
 Description: With vga digital clock, through the serial port can control the time display
 Downloaders recently: [More information of uploader 杨玉强 ]
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File list (Check if you may need any files): 
FilenameSizeDate
vga_7_0728\man.coe 1027 2017-07-28

vga_7_0728\vga_2_0725.cache\wt\java_command_handlers.wdf 547 2017-08-09

vga_7_0728\vga_2_0725.cache\wt\project.wpc 62 2017-08-09

vga_7_0728\vga_2_0725.cache\wt\synthesis.wdf 3749 2017-07-28

vga_7_0728\vga_2_0725.cache\wt\synthesis_details.wdf 100 2017-07-28

vga_7_0728\vga_2_0725.cache\wt\webtalk_pa.xml 1610 2017-08-09

vga_7_0728\vga_2_0725.hw\hw_1\hw.xml 683 2017-07-28

vga_7_0728\vga_2_0725.hw\vga_2_0725.lpr 343 2017-07-25

vga_7_0728\vga_2_0725.hw\webtalk\.xsim_webtallk.info 59 2017-07-28

vga_7_0728\vga_2_0725.hw\webtalk\labtool_webtalk.log 371 2017-07-28

vga_7_0728\vga_2_0725.hw\webtalk\usage_statistics_ext_labtool.html 3512 2017-07-28

vga_7_0728\vga_2_0725.hw\webtalk\usage_statistics_ext_labtool.xml 3108 2017-07-28

vga_7_0728\vga_2_0725.ip_user_files\ip\clk_wiz_0\clk_wiz_0.veo 3641 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\ip\vga_rom\vga_rom.veo 2966 2017-07-28

vga_7_0728\vga_2_0725.ip_user_files\ip\vga_rom\vga_rom.vho 3203 2017-07-28

vga_7_0728\vga_2_0725.ip_user_files\ipstatic\blk_mem_gen_v8_3_1\simulation\blk_mem_gen_v8_3.vhd 222214 2017-07-26

vga_7_0728\vga_2_0725.ip_user_files\ipstatic\dist_mem_gen_v8_0_9\simulation\dist_mem_gen_v8_0.vhd 27893 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\mem_init_files\dist_mem_gen_0.mif 4160 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\mem_init_files\man.coe 1027 2017-07-28

vga_7_0728\vga_2_0725.ip_user_files\mem_init_files\summary.log 900 2017-07-28

vga_7_0728\vga_2_0725.ip_user_files\mem_init_files\vga.coe 1278 2017-07-26

vga_7_0728\vga_2_0725.ip_user_files\mem_init_files\vga_rom.mif 1632 2017-07-28

vga_7_0728\vga_2_0725.ip_user_files\README.txt 130 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\ies\clk_wiz_0.sh 7015 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\ies\filelist.f 144 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\ies\filelist_irun.f 240 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\ies\file_info.txt 516 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\ies\glbl.v 1470 2015-11-18

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\ies\README.txt 2478 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\ies\simulate.do 158 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.sh 5593 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.udo

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\compile.do 320 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\filelist.f 144 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\file_info.txt 516 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\glbl.v 1470 2015-11-18

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\README.txt 2478 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\simulate.do 304 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\modelsim\wave.do 32 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.sh 5710 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.udo

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\compile.do 314 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\elaborate.do 176 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\filelist.f 144 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\file_info.txt 516 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\glbl.v 1470 2015-11-18

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\README.txt 2478 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\simulate.do 195 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\questa\wave.do 32 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\README.txt 3236 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\vcs\clk_wiz_0.sh 6949 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\vcs\filelist.f 144 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\vcs\file_info.txt 516 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\vcs\glbl.v 1470 2015-11-18

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\vcs\README.txt 2478 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\vcs\simulate.do 11 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\xsim\clk_wiz_0.sh 4754 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\xsim\cmd.tcl 464 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\xsim\filelist.f 144 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\xsim\file_info.txt 516 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\xsim\glbl.v 1470 2015-11-18

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\xsim\README.txt 2478 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\clk_wiz_0\xsim\vlog.prj 233 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\dist_mem_gen_0.mif 4160 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\dist_mem_gen_0.sh 7105 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\filelist.f 154 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\filelist_irun.f 253 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\file_info.txt 453 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\README.txt 2503 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\simulate.do 158 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\ies\vga.coe 1278 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\compile.do 424 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\dist_mem_gen_0.mif 4160 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\dist_mem_gen_0.sh 5678 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\dist_mem_gen_0.udo

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\filelist.f 154 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\file_info.txt 453 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\README.txt 2503 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\simulate.do 286 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\vga.coe 1278 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\modelsim\wave.do 12 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\compile.do 416 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\dist_mem_gen_0.mif 4160 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\dist_mem_gen_0.sh 5795 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\dist_mem_gen_0.udo

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\elaborate.do 158 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\filelist.f 154 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\file_info.txt 453 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\README.txt 2503 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\simulate.do 205 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\vga.coe 1278 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\questa\wave.do 12 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\README.txt 3236 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\vcs\dist_mem_gen_0.mif 4160 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\vcs\dist_mem_gen_0.sh 7060 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\vcs\filelist.f 154 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\vcs\file_info.txt 453 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\vcs\README.txt 2503 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\vcs\simulate.do 11 2017-07-25

vga_7_0728\vga_2_0725.ip_user_files\sim_scripts\dist_mem_gen_0_1\vcs\vga.coe 1278 2017-07-25

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