- Category:
- SCM
- Tags:
-
- File Size:
- 5kb
- Update:
- 2017-12-03
- Downloads:
- 0 Times
- Uploaded by:
- 林青
Description: Use Verilog to write time-division-second digital clocks for basic clocking.
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| digitial_clk\clock.v | 2205 | 2017-07-19
|
| digitial_clk\clock_top.v | 510 | 2017-07-19
|
| digitial_clk\data_dec_high_low.v | 1291 | 2017-07-18
|
| digitial_clk\decoder.v | 1180 | 2017-07-18
|
| digitial_clk\divider.v | 522 | 2017-07-18
|
| digitial_clk\lcd_play.v | 7205 | 2017-07-18
|
| digitial_clk\test.v | 530 | 2017-07-18
|
| digitial_clk\top.ucf | 493 | 2017-07-18
|
| digitial_clk\top.v | 1538 | 2017-07-18
|
| digitial_clk |
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