Title:
Clock_Synchronization_Module
Download
- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 240kb
- Update:
- 2017-12-08
- Downloads:
- 0 Times
- Uploaded by:
- 杨凯
Description: Design of medium frequency digital clock in digital receiver
Including Matlab simulation
Verilog, testbench code, and design documents
To Search:
File list (Check if you may need any files):
