- Category:
- Other systems
- Tags:
-
- File Size:
- 2kb
- Update:
- 2017-12-14
- Downloads:
- 0 Times
- Uploaded by:
- lijing
Description: Design of single chip CPU interface
Port definition:
Mbeb: interface type definition, 1 for Intel mode, 0 for moto mode
In the wr_rwb:intel mode, the low level is valid for writing; in the moto mode, the low level is valid for write, and the high level is effective for reading.
In the rd_eb:intel mode, the low level is valid for reading; in the moto mode, the high level is read allow.
A: address input, (5:0)
D: bi-directional data bus, (7:0)
Rd: low level internal circuit read effective
WR: low level internal circuit write effectiveness
Add: the read and write address of the internal circuit
Mbd_in:cpu writes the data in the internal register (7:0)
Mbd_out: internal circuit register readout values, sent to CPU (7:0)
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| 三讲练习二\cpu_intf.vhd | 3735 | 2016-09-26
|
| 三讲练习二\cpu_intf_TB.vhd | 4482 | 2016-09-26
|
| 三讲练习二 |
Download