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Title: project Download
  • Category:
  • Other systems
  • Tags:
  • File Size:
  • 42.63mb
  • Update:
  • 2017-12-18
  • Downloads:
  • 0 Times
  • Uploaded by:
  • 张扬
 Description: The complete FPGA routine, running on the platform, has a great help for beginners.
 Downloaders recently: [More information of uploader 张扬]
 To Search:
File list (Check if you may need any files): 
FilenameSizeDate
cy4BoardTest

cy4BoardTest\cy4.qpf 1272 2015-08-12

cy4BoardTest\cy4.qsf 9173 2015-08-22

cy4BoardTest\cy4.qws 1827 2015-08-22

cy4BoardTest\cy4_assignment_defaults.qdf 49805 2015-08-14

cy4BoardTest\ip_core

cy4BoardTest\ip_core\fifo

cy4BoardTest\ip_core\fifo\fifo_controller.qip 388 2015-08-14

cy4BoardTest\ip_core\fifo\fifo_controller.v 6681 2015-08-14

cy4BoardTest\ip_core\fifo\fifo_controller_bb.v 5670 2015-08-14

cy4BoardTest\ip_core\fifo\fifo_controller_inst.v 222 2015-08-14

cy4BoardTest\ip_core\fifo\greybox_tmp

cy4BoardTest\ip_core\fifo\greybox_tmp\cbx_args.txt 360 2015-08-14

cy4BoardTest\ip_core\fifo\rom_controller.qip

cy4BoardTest\ip_core\pll

cy4BoardTest\ip_core\pll\greybox_tmp

cy4BoardTest\ip_core\pll\greybox_tmp\cbx_args.txt 1695 2015-08-12

cy4BoardTest\ip_core\pll\pll_controller.ppf 696 2015-08-12

cy4BoardTest\ip_core\pll\pll_controller.qip 480 2015-08-12

cy4BoardTest\ip_core\pll\pll_controller.v 19568 2015-08-12

cy4BoardTest\ip_core\pll\pll_controller_bb.v 14973 2015-08-12

cy4BoardTest\ip_core\pll\pll_controller_inst.v 192 2015-08-12

cy4BoardTest\ip_core\rom

cy4BoardTest\ip_core\rom\greybox_tmp

cy4BoardTest\ip_core\rom\greybox_tmp\cbx_args.txt 356 2015-08-12

cy4BoardTest\ip_core\rom\rom_controller.qip 392 2015-08-14

cy4BoardTest\ip_core\rom\rom_controller.v 6716 2015-08-14

cy4BoardTest\ip_core\rom\rom_controller_bb.v 5235 2015-08-14

cy4BoardTest\ip_core\rom\rom_controller_inst.v 110 2015-08-14

cy4BoardTest\output_files

cy4BoardTest\output_files\cy4.asm.rpt 7147 2015-08-22

cy4BoardTest\output_files\cy4.cdf 378 2015-08-21

cy4BoardTest\output_files\cy4.done 26 2015-08-22

cy4BoardTest\output_files\cy4.eda.rpt 7616 2015-08-22

cy4BoardTest\output_files\cy4.fit.rpt 531229 2015-08-22

cy4BoardTest\output_files\cy4.fit.smsg 703 2015-08-22

cy4BoardTest\output_files\cy4.fit.summary 609 2015-08-22

cy4BoardTest\output_files\cy4.flow.rpt 10821 2015-08-22

cy4BoardTest\output_files\cy4.jdi 221 2015-08-22

cy4BoardTest\output_files\cy4.map.rpt 180697 2015-08-22

cy4BoardTest\output_files\cy4.map.summary 469 2015-08-22

cy4BoardTest\output_files\cy4.pin 20170 2015-08-22

cy4BoardTest\output_files\cy4.sof 358638 2015-08-22

cy4BoardTest\output_files\cy4.sta.rpt 1089210 2015-08-22

cy4BoardTest\output_files\cy4.sta.summary 3020 2015-08-22

cy4BoardTest\output_files\cy4_test.jic 524510 2015-08-21

cy4BoardTest\output_files\cy4_test.map 189 2015-08-21

cy4BoardTest\PLLJ_PLLSPE_INFO.txt 156 2015-08-22

cy4BoardTest\simulation

cy4BoardTest\simulation\modelsim

cy4BoardTest\simulation\modelsim\cy4.sft 323 2015-08-22

cy4BoardTest\simulation\modelsim\cy4.vo 1186042 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_8_1200mv_0c_slow.vo 1186059 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_8_1200mv_0c_v_slow.sdo 740734 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_8_1200mv_85c_slow.vo 1186060 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_8_1200mv_85c_v_slow.sdo 741392 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_min_1200mv_0c_fast.vo 1186061 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_min_1200mv_0c_v_fast.sdo 722326 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_modelsim.xrf 141023 2015-08-22

cy4BoardTest\simulation\modelsim\cy4_v.sdo 741392 2015-08-22

cy4BoardTest\source_code

cy4BoardTest\source_code\adc_controller.v 3489 2015-08-25

cy4BoardTest\source_code\beep.v 1143 2015-08-25

cy4BoardTest\source_code\cy4.v 11927 2015-08-25

cy4BoardTest\source_code\dac_controller.v 4504 2015-08-25

cy4BoardTest\source_code\greybox_tmp

cy4BoardTest\source_code\greybox_tmp\cbx_args.txt 356 2015-08-14

cy4BoardTest\source_code\iic_controller.v 6582 2015-08-25

cy4BoardTest\source_code\key_check.v 2444 2015-08-25

cy4BoardTest\source_code\lcd_controller.v 9340 2015-08-25

cy4BoardTest\source_code\led_controller.v 1355 2015-08-25

cy4BoardTest\source_code\my_uart_rx.v 3679 2015-08-25

cy4BoardTest\source_code\my_uart_tx.v 2009 2015-06-09

cy4BoardTest\source_code\para_define.v 477 2015-07-03

cy4BoardTest\source_code\rom_init.mif 12815 2015-08-14

cy4BoardTest\source_code\rtc_controller.v 6387 2015-06-20

cy4BoardTest\source_code\rtc_top.v 2855 2015-08-25

cy4BoardTest\source_code\seg7.v 3171 2015-08-25

cy4BoardTest\source_code\speed_setting.v 1887 2015-08-25

cy4BoardTest\source_code\sram_controller.v 4411 2015-08-25

cy4BoardTest\source_code\test_timing.v 4236 2015-08-25

cy4ex1

cy4ex10

cy4ex10\cy4.qpf 1272 2015-08-12

cy4ex10\cy4.qsf 5294 2015-08-18

cy4ex10\cy4.qws 1250 2015-08-22

cy4ex10\db

cy4ex10\db\cy4.db_info 140 2015-08-22

cy4ex10\db\cy4.ipinfo 163 2015-08-22

cy4ex10\db\cy4.sld_design_entry.sci 277 2015-08-22

cy4ex10\output_files

cy4ex10\output_files\cy4.done 26 2015-08-18

cy4ex10\output_files\cy4.fit.smsg 703 2015-08-18

cy4ex10\output_files\cy4.jdi 221 2015-08-18

cy4ex10\output_files\cy4.pin 20170 2015-08-18

cy4ex10\output_files\cy4.sof 358638 2015-08-18

cy4ex10\source_code

cy4ex10\source_code\arykeyscan.v 5564 2017-03-13

cy4ex10\source_code\cy4.v 1928 2015-08-25

cy4ex10\source_code\seg7.v 3227 2017-03-13

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