- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2017-12-22
- Downloads:
- 0 Times
- Uploaded by:
- 李鉴
Description: The combined logic and timing logic of the 3-8 decoders are implemented. The correctness has already passed through the simulation verification, the code specification
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| decoder3to8_2.v | 695 | 2017-10-21
|
| test_decoder3to8.v | 410 | 2017-10-22
|
| decoder3to8_1.v | 681 | 2017-10-22 |
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