Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: CommunicationICdesign Download
 Description: Communication IC design of the annex which is the communication IC design The chapters of the book are very detailed in the source code is conducive to fpga communication development
 Downloaders recently: [More information of uploader 许睿]
 To Search:
File list (Check if you may need any files):
FilenameSizeDate
通信IC设计\完整的几个工程\Altera_多种算法的说明和源码(CORDICECC8B10BAES)\arbitration\arbiter.v
..........\..............\.................................................\...........\arbiter_tb.v
..........\..............\.................................................\...........\bitscan.v
..........\..............\.................................................\...........\bitscan_tb.v
..........\..............\.................................................\...........\log2.inc
..........\..............\.................................................\...........\prio_encode.cpp
..........\..............\.................................................\...........\prio_encode.v
..........\..............\.................................................\...........\tx_4channel_arbiter.v
..........\..............\.................................................\...........\tx_4channel_arbiter_tb.sv
..........\..............\.................................................\..ithmetic\adder_tree.v
..........\..............\.................................................\..........\adder_tree_layer.v
..........\..............\.................................................\..........\adder_tree_node.v
..........\..............\.................................................\..........\adder_tree_tb.v
..........\..............\.................................................\..........\addsub.v
..........\..............\.................................................\..........\basic_adder.v
..........\..............\.................................................\..........\compress_32.v
..........\..............\.................................................\..........\cordic.v
..........\..............\.................................................\..........\cordic_angle_table.cpp
..........\..............\.................................................\..........\cordic_tb.v
..........\..............\.................................................\..........\divider.v
..........\..............\.................................................\..........\divider_tb.v
..........\..............\.................................................\..........\double_addsub.v
..........\..............\.................................................\..........\double_addsub_tb.v
..........\..............\.................................................\..........\iter_addsub.v
..........\..............\.................................................\..........\karatsuba_mult.v
..........\..............\.................................................\..........\karatsuba_mult_tb.v
..........\..............\.................................................\..........\lc_mult_signed.v
..........\..............\.................................................\..........\lc_mult_signed_tb.v
..........\..............\.................................................\..........\log2.inc
..........\..............\.................................................\..........\make_comp.cpp
..........\..............\.................................................\..........\make_sum.cpp
..........\..............\.................................................\..........\mult_3tick.v
..........\..............\.................................................\..........\mult_shift.v
..........\..............\.................................................\..........\mult_shift_tb.v
..........\..............\.................................................\..........\pipeline_add.v
..........\..............\.................................................\..........\pipeline_add_msb.v
..........\..............\.................................................\..........\pipeline_add_tb.v
..........\..............\.................................................\..........\select_add.v
..........\..............\.................................................\..........\select_add_speed_test.v
..........\..............\.................................................\..........\six_three_

CodeBus www.codebus.net