Description: On the BCH encoder and decoder, can achieve 16-bit, 32-bit, 64-bit, 128-bit encoding and decoding error correction, 2-bit error correction, Verilog implementation
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bch_dec_enc_dcd
...............\doc
...............\...\bch_dec_dcd.pdf
...............\rtl
...............\...\univ
...............\...\....\bch_dec_dcd_univ_top.v
...............\...\....\bch_dec_enc_univ_top.v
...............\...\....\bch_dec_fn.v
...............\...\....\enc_synd_calc_univ.v
...............\...\....\enc_synd_gen_fn_127.v
...............\...\....\enc_synd_gen_fn_255.v
...............\...\....\enc_synd_gen_fn_31.v
...............\...\....\enc_synd_gen_fn_63.v
...............\...\....\err_patt_dcd_fn_127.v
...............\...\....\err_patt_dcd_fn_255.v
...............\...\....\err_patt_dcd_fn_31.v
...............\...\....\err_patt_dcd_fn_63.v
...............\...\....\err_pat_dcd_rom_univ.v
...............\...\....\tags
...............\...\....\timescale.v
...............\sim
...............\...\univ
...............\...\....\dcd_univ_tb_top_n.v
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