Description: The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance.
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File list (Check if you may need any files):
laoweng16
.........\.Xil
.........\1+2+...+100.coe
.........\22cheng-11.coe
.........\ALU_ACC.lso
.........\ALU_ACC.prj
.........\ALU_ACC.stx
.........\alu_acc.vhd
.........\ALU_ACC.xst
.........\ALU_ACC_beh.prj
.........\ALU_ACC_isim_beh.exe
.........\ALU_ACC_isim_beh.wdb
.........\ALU_ACC_isim_beh1.wdb
.........\br.vhd
.........\clk_div.vhd
.........\cu.vhd
.........\digital.lso
.........\digital.prj
.........\digital.stx
.........\digital.vhd
.........\digital.xst
.........\fuse.log
.........\fuse.xmsgs
.........\fuseRelaunch.cmd
.........\impact.xsl
.........\impact_impact.xwbt
.........\ipcore_dir
.........\..........\coregen.cgp
.........\..........\coregen.log
.........\..........\create_RAM.tcl
.........\..........\create_rom.tcl
.........\..........\edit_rom.tcl
.........\..........\gen_RAM.tcl
.........\..........\RAM
.........\..........\RAM.asy
.........\..........\RAM.gise
.........\..........\RAM.mif
.........\..........\RAM.ngc
.........\..........\RAM.sym
.........\..........\RAM.v
.........\..........\RAM.veo
.........\..........\RAM.xco
.........\..........\RAM.xise
.........\..........\...\dist_mem_gen_v7_2_readme.txt
.........\..........\...\doc
.........\..........\...\...\dist_mem_gen_v7_2_vinfo.html
.........\..........\...\...\pg063-dist-mem-gen.pdf
.........\..........\...\example_design
.........\..........\...\..............\RAM_exdes.ucf
.........\..........\...\..............\RAM_exdes.vhd
.........\..........\...\..............\RAM_exdes.xdc
.........\..........\...\..............\RAM_prod_exdes.vhd
.........\..........\...\implement
.........\..........\...\.........\implement.bat
.........\..........\...\.........\implement.sh
.........\..........\...\.........\implement_synplify.bat
.........\..........\...\.........\implement_synplify.sh
.........\..........\...\.........\planAhead_ise.bat
.........\..........\...\.........\planAhead_ise.sh
.........\..........\...\.........\planAhead_ise.tcl
.........\..........\...\.........\xst.prj
.........\..........\...\.........\xst.scr
.........\..........\...\simulation
.........\..........\...\..........\functional
.........\..........\...\..........\..........\simulate_mti.bat
.........\..........\...\..........\..........\simulate_mti.do
.........\..........\...\..........\..........\simulate_mti.sh
.........\..........\...\..........\RAM_tb.vhd
.........\..........\...\..........\RAM_tb_agen.vhd
.........\..........\...\..........\RAM_tb_checker.vhd
.........\..........\...\..........\RAM_tb_dgen.vhd
.........\..........\...\..........\RAM_tb_pkg.vhd
.........\..........\...\..........\RAM_tb_rng.vhd
.........\..........\...\..........\RAM_tb_stim_gen.vhd
.........\..........\...\..........\RAM_tb_synth.vhd
.........\..........\...\..........\timing
.........\..........\...\..........\......\simulate_mti.bat
.........\..........\...\..........\......\simulate_mti.do
.........\..........\...\..........\......\simulate_mti.sh
.........\..........\RAM_flist.txt
.........\..........\RAM_xmdf.tcl
.........\..........\rom
.........\..........\rom.asy
.........\..........\rom.gise
.........\..........\rom.mif
.........\..........\rom.ncf
.........\..........\rom.ngc
.........\..........\rom.sym
.........\..........\rom.v
.........\..........\rom.veo
.........\..........\rom.xco
.........\..........\rom.xise
.........\..........\...\dist_mem_gen_v7_2_readme.txt
.........\..........\...\doc
.........\..........\...\...\dist_mem_gen_v7_2_vinfo.html
.........\..........\...\...\pg063-dist-mem-gen.pdf
.........\..........\...\example_design
.........\..........\...\..............\rom_exdes.ucf
.........\..........\...\..............\rom_exdes.vhd
.........\..........\...\..............\rom_exdes.xdc
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