Description: (2) the use of serial port to achieve the receiving function, and the received characters through the serial port to send to the serial port on the computer (1) the use of serial port to achieve the sending function, that is, the use of computer serial debugging small assistant timer display HELLO WORLD words Debugging small assistant display, for example: the use of serial communication assistant to send the function to the serial port to send Good Good Study, day day up , and then use the FPGA to achieve forwarding, the characters sent back the serial port debugging small assistant display.
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File list (Check if you may need any files):
clk_div
.......\clk_div.bsf
.......\clk_div.qpf
.......\clk_div.qsf
.......\clk_div.qws
.......\clk_div.vhd
.......\clk_div.vwf
.......\clk_div.vwf.temp
.......\clk_div_nativelink_simulation.rpt
.......\db
.......\..\clk_div.asm.qmsg
.......\..\clk_div.asm.rdb
.......\..\clk_div.asm_labs.ddb
.......\..\clk_div.cbx.xml
.......\..\clk_div.cmp.bpm
.......\..\clk_div.cmp.cdb
.......\..\clk_div.cmp.hdb
.......\..\clk_div.cmp.idb
.......\..\clk_div.cmp.kpt
.......\..\clk_div.cmp.logdb
.......\..\clk_div.cmp.rdb
.......\..\clk_div.cmp0.ddb
.......\..\clk_div.cmp1.ddb
.......\..\clk_div.cmp2.ddb
.......\..\clk_div.cmp_merge.kpt
.......\..\clk_div.db_info
.......\..\clk_div.eda.qmsg
.......\..\clk_div.eds_overflow
.......\..\clk_div.epe.qmsg
.......\..\clk_div.fit.qmsg
.......\..\clk_div.fnsim.hdb
.......\..\clk_div.fnsim.qmsg
.......\..\clk_div.hier_info
.......\..\clk_div.hif
.......\..\clk_div.ipinfo
.......\..\clk_div.lpc.html
.......\..\clk_div.lpc.rdb
.......\..\clk_div.lpc.txt
.......\..\clk_div.map.ammdb
.......\..\clk_div.map.bpm
.......\..\clk_div.map.cdb
.......\..\clk_div.map.hdb
.......\..\clk_div.map.kpt
.......\..\clk_div.map.logdb
.......\..\clk_div.map.qmsg
.......\..\clk_div.map.rdb
.......\..\clk_div.map_bb.cdb
.......\..\clk_div.map_bb.hdb
.......\..\clk_div.map_bb.logdb
.......\..\clk_div.pplq.rdb
.......\..\clk_div.pre_map.hdb
.......\..\clk_div.pti_db_list.ddb
.......\..\clk_div.root_partition.map.reg_db.cdb
.......\..\clk_div.routing.rdb
.......\..\clk_div.rtlv.hdb
.......\..\clk_div.rtlv_sg.cdb
.......\..\clk_div.rtlv_sg_swap.cdb
.......\..\clk_div.sgdiff.cdb
.......\..\clk_div.sgdiff.hdb
.......\..\clk_div.sim.hdb
.......\..\clk_div.sim.qmsg
.......\..\clk_div.sim.rdb
.......\..\clk_div.sim.vwf
.......\..\clk_div.simfam
.......\..\clk_div.sld_design_entry.sci
.......\..\clk_div.sld_design_entry_dsc.sci
.......\..\clk_div.smart_action.txt
.......\..\clk_div.sta.qmsg
.......\..\clk_div.sta.rdb
.......\..\clk_div.sta_cmp.8_slow.tdb
.......\..\clk_div.syn_hier_info
.......\..\clk_div.tis_db_list.ddb
.......\..\clk_div.vpr.ammdb
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_clk_div.qmsg
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\...................\clk_div.db_info
.......\..............\...................\clk_div.root_partition.cmp.ammdb
.......\..............\...................\clk_div.root_partition.cmp.cdb
.......\..............\...................\clk_div.root_partition.cmp.dfp
.......\..............\...................\clk_div.root_partition.cmp.hdb
.......\..............\...................\clk_div.root_partition.cmp.kpt
.......\..............\...................\clk_div.root_partition.cmp.logdb
.......\..............\...................\clk_div.root_partition.cmp.rcfdb
.......\..............\...................\clk_div.root_partition.map.cdb
.......\..............\...................\clk_div.root_partition.map.dpi
.......\..............\...................\clk_div.root_partition.map.hbdb.cdb
.......\..............\...................\clk_div.root_partition.map.hbdb.hb_info
.......\..............\...................\clk_div.root_partition.map.hbdb.hdb
.......\..............\...................\clk_div.root_partition.map.hbdb.sig
.......\..............\...................\clk_div.root_partition.map.hdb
.......\..............\...................\clk_div.root_partition.map.kpt
.......\..............\README
.......\output_files
.......\............\clk_div.asm.rpt
.......\............\clk_div.cdf
.......\............\clk_div.done
.......\............\clk_div.eda.rpt
.......\............\clk_div.fit.rpt
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