Description: Through FPGA and AD9708 high speed DA module, adjustable frequency Fang Bo, sine wave, triangle wave
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File list (Check if you may need any files):
AD9708
AD9708\AD9708.asm.rpt
AD9708\AD9708.bdf
AD9708\AD9708.cdf
AD9708\AD9708.done
AD9708\AD9708.eda.rpt
AD9708\AD9708.fit.rpt
AD9708\AD9708.fit.smsg
AD9708\AD9708.fit.summary
AD9708\AD9708.flow.rpt
AD9708\AD9708.jdi
AD9708\AD9708.map
AD9708\AD9708.map.rpt
AD9708\AD9708.map.smsg
AD9708\AD9708.map.summary
AD9708\AD9708.pin
AD9708\AD9708.pof
AD9708\AD9708.qpf
AD9708\AD9708.qsf
AD9708\AD9708.qws
AD9708\AD9708.sof
AD9708\AD9708.sta.rpt
AD9708\AD9708.sta.summary
AD9708\PLLJ_PLLSPE_INFO.txt
AD9708\add_32bit.bsf
AD9708\add_32bit.v
AD9708\db
AD9708\db\AD9708.amm.cdb
AD9708\db\AD9708.asm.qmsg
AD9708\db\AD9708.asm.rdb
AD9708\db\AD9708.asm_labs.ddb
AD9708\db\AD9708.cbx.xml
AD9708\db\AD9708.cmp.bpm
AD9708\db\AD9708.cmp.cdb
AD9708\db\AD9708.cmp.hdb
AD9708\db\AD9708.cmp.kpt
AD9708\db\AD9708.cmp.logdb
AD9708\db\AD9708.cmp.rdb
AD9708\db\AD9708.cmp_merge.kpt
AD9708\db\AD9708.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
AD9708\db\AD9708.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
AD9708\db\AD9708.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
AD9708\db\AD9708.db_info
AD9708\db\AD9708.eda.qmsg
AD9708\db\AD9708.fit.qmsg
AD9708\db\AD9708.hier_info
AD9708\db\AD9708.hif
AD9708\db\AD9708.idb.cdb
AD9708\db\AD9708.lpc.html
AD9708\db\AD9708.lpc.rdb
AD9708\db\AD9708.lpc.txt
AD9708\db\AD9708.map.bpm
AD9708\db\AD9708.map.cdb
AD9708\db\AD9708.map.hdb
AD9708\db\AD9708.map.kpt
AD9708\db\AD9708.map.logdb
AD9708\db\AD9708.map.qmsg
AD9708\db\AD9708.map.rdb
AD9708\db\AD9708.map_bb.cdb
AD9708\db\AD9708.map_bb.hdb
AD9708\db\AD9708.map_bb.logdb
AD9708\db\AD9708.pre_map.cdb
AD9708\db\AD9708.pre_map.hdb
AD9708\db\AD9708.root_partition.map.reg_db.cdb
AD9708\db\AD9708.routing.rdb
AD9708\db\AD9708.rtlv.hdb
AD9708\db\AD9708.rtlv_sg.cdb
AD9708\db\AD9708.rtlv_sg_swap.cdb
AD9708\db\AD9708.sgdiff.cdb
AD9708\db\AD9708.sgdiff.hdb
AD9708\db\AD9708.sld_design_entry.sci
AD9708\db\AD9708.sld_design_entry_dsc.sci
AD9708\db\AD9708.smart_action.txt
AD9708\db\AD9708.sta.qmsg
AD9708\db\AD9708.sta.rdb
AD9708\db\AD9708.sta_cmp.8_slow_1200mv_85c.tdb
AD9708\db\AD9708.syn_hier_info
AD9708\db\AD9708.tis_db_list.ddb
AD9708\db\AD9708.tiscmp.fast_1200mv_0c.ddb
AD9708\db\AD9708.tiscmp.fastest_slow_1200mv_0c.ddb
AD9708\db\AD9708.tiscmp.fastest_slow_1200mv_85c.ddb
AD9708\db\AD9708.tiscmp.slow_1200mv_0c.ddb
AD9708\db\AD9708.tiscmp.slow_1200mv_85c.ddb
AD9708\db\AD9708.tmw_info
AD9708\db\altsyncram_t091.tdf
AD9708\db\logic_util_heursitic.dat
AD9708\db\pll_altpll.v
AD9708\db\prev_cmp_AD9708.qmsg
AD9708\delay_soft.v
AD9708\delay_soft.v.bak
AD9708\greybox_tmp
AD9708\greybox_tmp\cbx_args.txt
AD9708\incremental_db
AD9708\incremental_db\README
AD9708\incremental_db\compiled_partitions
AD9708\incremental_db\compiled_partitions\AD9708.db_info
AD9708\incremental_db\compiled_partitions\AD9708.root_partition.cmp.cdb
AD9708\incremental_db\compiled_partitions\AD9708.root_partition.cmp.dfp
AD9708\incremental_db\compiled_partitions\AD9708.root_partition.cmp.hdb
AD9708\incremental_db\compiled_partitions\AD9708.root_partition.cmp.kpt