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Title: CPU_Verilog Download
 Description: This code completes the design of pipelined CPU
 Downloaders recently: [More information of uploader 樊子辰 ]
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File list (Check if you may need any files):
ALU.v
compare.v
control.v
CPU.v
CPU_pipe.v
DataMem.v
Forward.v
Hazard.v
Peripheral.v
p_reg.v
regfile.v
rom.v
top.v
UART.v

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