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Title: m60v20161109 Download
 Description: Using Verilog language to achieve the modulus of 60 counters, compiled by qualified, using quarter2 and above can be used directly
 Downloaders recently: [More information of uploader 赵海博 ]
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File list (Check if you may need any files):
cffsd2\db\lab02.asm.qmsg
cffsd2\db\lab02.asm_labs.ddb
cffsd2\db\lab02.cbx.xml
cffsd2\db\lab02.cmp.cdb
cffsd2\db\lab02.cmp.hdb
cffsd2\db\lab02.cmp.kpt
cffsd2\db\lab02.cmp.logdb
cffsd2\db\lab02.cmp.rdb
cffsd2\db\lab02.cmp.tdb
cffsd2\db\lab02.cmp0.ddb
cffsd2\db\lab02.dbp
cffsd2\db\lab02.db_info
cffsd2\db\lab02.eco.cdb
cffsd2\db\lab02.eds_overflow
cffsd2\db\lab02.fit.qmsg
cffsd2\db\lab02.fnsim.hdb
cffsd2\db\lab02.fnsim.qmsg
cffsd2\db\lab02.hier_info
cffsd2\db\lab02.hif
cffsd2\db\lab02.map.cdb
cffsd2\db\lab02.map.hdb
cffsd2\db\lab02.map.logdb
cffsd2\db\lab02.map.qmsg
cffsd2\db\lab02.pre_map.cdb
cffsd2\db\lab02.pre_map.hdb
cffsd2\db\lab02.psp
cffsd2\db\lab02.rtlv.hdb
cffsd2\db\lab02.rtlv_sg.cdb
cffsd2\db\lab02.rtlv_sg_swap.cdb
cffsd2\db\lab02.sgdiff.cdb
cffsd2\db\lab02.sgdiff.hdb
cffsd2\db\lab02.signalprobe.cdb
cffsd2\db\lab02.sim.hdb
cffsd2\db\lab02.sim.qmsg
cffsd2\db\lab02.sim.rdb
cffsd2\db\lab02.sim.vwf
cffsd2\db\lab02.sld_design_entry.sci
cffsd2\db\lab02.sld_design_entry_dsc.sci
cffsd2\db\lab02.syn_hier_info
cffsd2\db\lab02.tan.qmsg
cffsd2\db\wed.zsf
cffsd2\lab02.asm.rpt
cffsd2\lab02.cdf
cffsd2\lab02.done
cffsd2\lab02.dpf
cffsd2\lab02.fit.rpt
cffsd2\lab02.fit.smsg
cffsd2\lab02.fit.summary
cffsd2\lab02.flow.rpt
cffsd2\lab02.map.rpt
cffsd2\lab02.map.smsg
cffsd2\lab02.map.summary
cffsd2\lab02.pin
cffsd2\lab02.pof
cffsd2\lab02.qpf
cffsd2\lab02.qsf
cffsd2\lab02.qws
cffsd2\lab02.sim.rpt
cffsd2\lab02.sof
cffsd2\lab02.tan.rpt
cffsd2\lab02.tan.summary
cffsd2\lab02.v
cffsd2\lab02.vwf
cffsd2\db
cffsd2

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