DE2_115_VGA_20170716
DE2_115_VGA_20170716\db
DE2_115_VGA_20170716\db\.cmp.kpt
DE2_115_VGA_20170716\db\DE2_115_VGA.asm.qmsg
DE2_115_VGA_20170716\db\DE2_115_VGA.asm.rdb
DE2_115_VGA_20170716\db\DE2_115_VGA.asm_labs.ddb
DE2_115_VGA_20170716\db\DE2_115_VGA.cbx.xml
DE2_115_VGA_20170716\db\DE2_115_VGA.cmp.bpm
DE2_115_VGA_20170716\db\DE2_115_VGA.cmp.cdb
DE2_115_VGA_20170716\db\DE2_115_VGA.cmp.hdb
DE2_115_VGA_20170716\db\DE2_115_VGA.cmp.idb
DE2_115_VGA_20170716\db\DE2_115_VGA.cmp.logdb
DE2_115_VGA_20170716\db\DE2_115_VGA.cmp.rdb
DE2_115_VGA_20170716\db\DE2_115_VGA.cmp_merge.kpt
DE2_115_VGA_20170716\db\DE2_115_VGA.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
DE2_115_VGA_20170716\db\DE2_115_VGA.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
DE2_115_VGA_20170716\db\DE2_115_VGA.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
DE2_115_VGA_20170716\db\DE2_115_VGA.db_info
DE2_115_VGA_20170716\db\DE2_115_VGA.fit.qmsg
DE2_115_VGA_20170716\db\DE2_115_VGA.hier_info
DE2_115_VGA_20170716\db\DE2_115_VGA.hif
DE2_115_VGA_20170716\db\DE2_115_VGA.ipinfo
DE2_115_VGA_20170716\db\DE2_115_VGA.lpc.html
DE2_115_VGA_20170716\db\DE2_115_VGA.lpc.rdb
DE2_115_VGA_20170716\db\DE2_115_VGA.lpc.txt
DE2_115_VGA_20170716\db\DE2_115_VGA.map.ammdb
DE2_115_VGA_20170716\db\DE2_115_VGA.map.bpm
DE2_115_VGA_20170716\db\DE2_115_VGA.map.cdb
DE2_115_VGA_20170716\db\DE2_115_VGA.map.hdb
DE2_115_VGA_20170716\db\DE2_115_VGA.map.kpt
DE2_115_VGA_20170716\db\DE2_115_VGA.map.logdb
DE2_115_VGA_20170716\db\DE2_115_VGA.map.qmsg
DE2_115_VGA_20170716\db\DE2_115_VGA.map.rdb
DE2_115_VGA_20170716\db\DE2_115_VGA.map_bb.cdb
DE2_115_VGA_20170716\db\DE2_115_VGA.map_bb.hdb
DE2_115_VGA_20170716\db\DE2_115_VGA.map_bb.logdb
DE2_115_VGA_20170716\db\DE2_115_VGA.npp.qmsg
DE2_115_VGA_20170716\db\DE2_115_VGA.pre_map.hdb
DE2_115_VGA_20170716\db\DE2_115_VGA.pti_db_list.ddb
DE2_115_VGA_20170716\db\DE2_115_VGA.root_partition.map.reg_db.cdb
DE2_115_VGA_20170716\db\DE2_115_VGA.routing.rdb
DE2_115_VGA_20170716\db\DE2_115_VGA.rtlv.hdb
DE2_115_VGA_20170716\db\DE2_115_VGA.rtlv_sg.cdb
DE2_115_VGA_20170716\db\DE2_115_VGA.rtlv_sg_swap.cdb
DE2_115_VGA_20170716\db\DE2_115_VGA.sgate.nvd
DE2_115_VGA_20170716\db\DE2_115_VGA.sgate_sm.nvd
DE2_115_VGA_20170716\db\DE2_115_VGA.sgdiff.cdb
DE2_115_VGA_20170716\db\DE2_115_VGA.sgdiff.hdb
DE2_115_VGA_20170716\db\DE2_115_VGA.sld_design_entry.sci
DE2_115_VGA_20170716\db\DE2_115_VGA.sld_design_entry_dsc.sci
DE2_115_VGA_20170716\db\DE2_115_VGA.smart_action.txt
DE2_115_VGA_20170716\db\DE2_115_VGA.sta.qmsg
DE2_115_VGA_20170716\db\DE2_115_VGA.sta.rdb
DE2_115_VGA_20170716\db\DE2_115_VGA.sta_cmp.7_slow_1200mv_85c.tdb
DE2_115_VGA_20170716\db\DE2_115_VGA.tiscmp.fast_1200mv_0c.ddb
DE2_115_VGA_20170716\db\DE2_115_VGA.tiscmp.slow_1200mv_0c.ddb
DE2_115_VGA_20170716\db\DE2_115_VGA.tiscmp.slow_1200mv_85c.ddb
DE2_115_VGA_20170716\db\DE2_115_VGA.tis_db_list.ddb
DE2_115_VGA_20170716\db\DE2_115_VGA.tmw_info
DE2_115_VGA_20170716\db\DE2_115_VGA.vpr.ammdb
DE2_115_VGA_20170716\db\logic_util_heursitic.dat
DE2_115_VGA_20170716\db\prev_cmp_DE2_115_VGA.qmsg
DE2_115_VGA_20170716\DE2_115_VGA.jdi
DE2_115_VGA_20170716\DE2_115_VGA.qpf
DE2_115_VGA_20170716\DE2_115_VGA.qsf
DE2_115_VGA_20170716\DE2_115_VGA.qws
DE2_115_VGA_20170716\DE2_115_VGA.v
DE2_115_VGA_20170716\DE2_115_VGA.v.bak
DE2_115_VGA_20170716\DE2_115_VGA_assignment_defaults.qdf
DE2_115_VGA_20170716\incremental_db
DE2_115_VGA_20170716\incremental_db\compiled_partitions
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.db_info
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.cmp.ammdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.cmp.cdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.cmp.dfp
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.cmp.hdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.cmp.kpt
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.cmp.logdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.cmp.rcfdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.cdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.dpi
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.hbdb.cdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.hbdb.hb_info
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.hbdb.hdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.hbdb.sig
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.hdb
DE2_115_VGA_20170716\incremental_db\compiled_partitions\DE2_115_VGA.root_partition.map.kpt
DE2_115_VGA_20170716\incremental_db\README
DE2_115_VGA_20170716\output_files
DE2_115_VGA_20170716\output_files\DE2_115_VGA.asm.rpt
DE2_115_VGA_20170716\output_files\DE2_115_VGA.done
DE2_115_VGA_20170716\output_files\DE2_115_VGA.fit.rpt
DE2_115_VGA_20170716\output_files\DE2_115_VGA.fit.smsg
DE2_115_VGA_20170716\output_files\DE2_115_VGA.fit.summary
DE2_115_VGA_20170716\output_files\DE2_115_VGA.flow.rpt
DE2_115_VGA_20170716\output_files\DE2_115_VGA.jdi
DE2_115_VGA_20170716\output_files\DE2_115_VGA.map.rpt
DE2_115_VGA_20170716\output_files\DE2_115_VGA.map.summary
DE2_115_VGA_20170716\output_files\DE2_115_VGA.pin
DE2_115_VGA_20170716\output_files\DE2_115_VGA.sof