Title:
无线通信FPGA设计[田耘等编著][程序源代码]
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Description: Wireless communication FPGA design, Tian Yun et al [source code], it is difficult to find all the code for wireless communication
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Verilog代码
Verilog代码\c10
Verilog代码\c10\10-2
Verilog代码\c10\10-2\mult.xco
Verilog代码\c10\10-2\mydds.xco
Verilog代码\c10\10-2\square_syn.v
Verilog代码\c10\10-4
Verilog代码\c10\10-4\coastas_dds.v
Verilog代码\c10\10-4\costas_lf.v
Verilog代码\c10\10-4\costas_loop.v
Verilog代码\c10\10-4\costas_lpf.v
Verilog代码\c10\10-4\costas_mult.v
Verilog代码\c10\10-4\err_mult.v
Verilog代码\c10\10-4\fir_lpf.xco
Verilog代码\c10\10-4\mult.xco
Verilog代码\c10\10-4\my_dds.xco
Verilog代码\c10\10-6
Verilog代码\c10\10-6\dearly_sub.v
Verilog代码\c10\10-6\dedds.v
Verilog代码\c10\10-6\delay_early_gate.v
Verilog代码\c10\10-6\de_mult.xco
Verilog代码\c10\10-6\eddds.xco
Verilog代码\c10\10-6\iir.v
Verilog代码\c10\10-6\iir1.v
Verilog代码\c10\10-8
Verilog代码\c10\10-8\baker.v
Verilog代码\c11
Verilog代码\c11\11-10
Verilog代码\c11\11-10\div16.xco
Verilog代码\c11\11-10\fir_rls.v
Verilog代码\c11\11-10\rlsmult.xco
Verilog代码\c11\11-10\shiftreg25.xco
Verilog代码\c11\11-10\shiftreg28.xco
Verilog代码\c11\11-10\shiftreg3.xco
Verilog代码\c11\11-12
Verilog代码\c11\11-12\dfe_filter.v
Verilog代码\c11\11-12\dfe_mult.xco
Verilog代码\c11\11-14
Verilog代码\c11\11-14\aa_adder.xco
Verilog代码\c11\11-14\aa_bram.xco
Verilog代码\c11\11-14\aa_cmult.xco
Verilog代码\c11\11-14\ad_a.v
Verilog代码\c11\11-14\shift16.xco
Verilog代码\c11\11-2
Verilog代码\c11\11-2\fir_lms.v
Verilog代码\c11\11-3
Verilog代码\c11\11-3\fir_pipline_lms.v
Verilog代码\c11\11-3\lmsmult.xco
Verilog代码\c11\11-5
Verilog代码\c11\11-5\mult.xco
Verilog代码\c11\11-5\shiftreg4.xco
Verilog代码\c11\11-5\sign_fir_lms.v
Verilog代码\c11\11-8
Verilog代码\c11\11-8\blockconnect.v
Verilog代码\c11\11-8\cmult.v
Verilog代码\c11\11-8\coe_updata.v
Verilog代码\c11\11-8\complex_mult.xco
Verilog代码\c11\11-8\fft_block.v
Verilog代码\c11\11-8\fft_block_lms.v
Verilog代码\c11\11-8\fft_w16_p32.xco
Verilog代码\c11\11-8\gonge.v
Verilog代码\c11\11-8\ifft_block.v
Verilog代码\c11\11-8\insert.v
Verilog代码\c11\11-8\save_sub.v
Verilog代码\c11\11-8\shiftreg.xco
Verilog代码\c11\11-8\shiftreg3.xco
Verilog代码\c11\11-8\shift_reg2.xco
Verilog代码\c11\11-8\srl16_w16_d16.xco
Verilog代码\c11\11-8\test_block_connect.v
Verilog代码\c12_0
Verilog代码\c12_0\12-2_0
Verilog代码\c12_0\12-4_0
Verilog代码\c12_0\12-6
Verilog代码\c12_0\12-6\rake_cmult.xco
Verilog代码\c12_0\12-6\rake_mrc.v
Verilog代码\c12_0\12-6\rake_shift4.xco
Verilog代码\c13
Verilog代码\c13\13-2
Verilog代码\c13\13-2\ovsf.v
Verilog代码\c13\13-3
Verilog代码\c13\13-3\Dscamb.v
Verilog代码\c13\13-6
Verilog代码\c13\13-6\adder_18vs18.xco
Verilog代码\c13\13-6\CPICH.v
Verilog代码\c13\13-6\ram_1024.xco
Verilog代码\c13\13-6\ram_descramb.xco
Verilog代码\c3
Verilog代码\c3\3-22
Verilog代码\c3\3-22\adder8.v
Verilog代码\c3\3-23
Verilog代码\c3\3-23\adder8_2.v
Verilog代码\c3\3-24
Verilog代码\c3\3-24\adder8_4.v
Verilog代码\c5
Verilog代码\c5\5-1
Verilog代码\c5\5-1\adder16_2.v
Verilog代码\c5\5-10
Verilog代码\c5\5-10\div16.xco
Verilog代码\c5\5-10\div16_1.v
Verilog代码\c5\5-11
