- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2017-08-08
- Downloads:
- 0 Times
- Uploaded by:
- 马玉奇
Description: UART serial communication module: including receiving module RXD, sending module TXD, frequency division module FREDIV
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TXD.vhd
FREDIV.vhd
RXD.vhd