- Category:
- VHDL-FPGA-Verilog
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- 1.39mb
- Update:
- 2017-12-28
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- 王飞
Description: (1) the abstract level of Verilog
The modular design of Verilog
How to select the correct data type for the port
(4) the generation of latch in Verilog language
Combinational logic feedback loop
The blocking and nonblocking assignment assignment different
The soul of state machine FPGA
The importance of the code style
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| Filename | Size | Date |
|---|
| 信号分析与处理——MATLAB语.pdf | 4574856 | 2007-10-28 |
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