| Filename | Size | Date |
|---|
| C402 V12硬件原理图及pcb源文件（altium10)\ALTERA CYCLONEIV FPGA C402 V11 20160426_FINAL.SCHLIB | 76288 | 2016-06-16
|
| C402 V12硬件原理图及pcb源文件（altium10)\ALTERA CYCLONEIV FPGA C402 V12 20160615.PcbLib | 103424 | 2016-06-16
|
| C402 V12硬件原理图及pcb源文件（altium10)\C402 V12.OutJob | 10895 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\C402 V12.PcbDoc | 2057216 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\C402 V12.PcbDoc.htm | 6030 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\C402 V12.PDF | 1164587 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\C402 V12.PrjPcb | 46571 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\C402 V12.PrjPcbStructure | 61 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\ALTERA CYCLONEIV FPGA C402 V11 20160426_FINAL.~(1).SCHLIB.Zip | 13342 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\ALTERA CYCLONEIV FPGA C402 V12 20160615.~(1).PcbLib.Zip | 14430 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\ALTERA CYCLONEIV FPGA C402 V12 20160615.~(2).PcbLib.Zip | 529598 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(1).PcbDoc.Zip | 745322 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(1).PrjPcb.Zip | 4363 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(2).PrjPcb.Zip | 5317 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(3).PrjPcb.Zip | 5317 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(4).PcbDoc.Zip | 800175 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(5).PcbDoc.Zip | 677049 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(6).PcbDoc.Zip | 800175 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(7).PcbDoc.Zip | 800435 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\C402 V12.~(8).PcbDoc.Zip | 716130 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE1 BLOCK DIAGRAM.~(1).SchDoc.Zip | 3054 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE2 FPGA IO&CLK.~(1).SchDoc.Zip | 15903 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE3 FPGA Config&PWR&J.~(1).SchDoc.Zip | 51659 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE3 FPGA Config&PWR&J.~(2).SchDoc.Zip | 51029 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE3 FPGA Config&PWR&J.~(3).SchDoc.Zip | 51028 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE3 FPGA Config&PWR&J.~(4).SchDoc.Zip | 51073 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE3 FPGA Config&PWR&J.~(5).SchDoc.Zip | 51111 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE3 FPGA Config&PWR&J.~(6).SchDoc.Zip | 51004 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE3 FPGA Config&PWR&J.~(7).SchDoc.Zip | 50859 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE4 Connector.~(1).SchDoc.Zip | 12853 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\History\PAGE4 Connector.~(2).SchDoc.Zip | 13268 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\PAGE1 BLOCK DIAGRAM.SchDoc | 14848 | 2016-06-16
|
| C402 V12硬件原理图及pcb源文件（altium10)\PAGE2 FPGA IO&CLK.SchDoc | 137216 | 2016-06-16
|
| C402 V12硬件原理图及pcb源文件（altium10)\PAGE3 FPGA Config&PWR&J.SchDoc | 485888 | 2016-06-16
|
| C402 V12硬件原理图及pcb源文件（altium10)\PAGE4 Connector.SchDoc | 111616 | 2016-06-16
|
| C402 V12硬件原理图及pcb源文件（altium10)\Project Logs for C402 V12\C402 V12 PCB ECO 2017-6-27 22-24-24.LOG | 4979 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\Project Logs for C402 V12\C402 V12 PCB ECO 2017-6-27 23-06-43.LOG | 4979 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\Project Logs for C402 V12\C402 V12.PrjPcb And C402 V12.XLS | 82748 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\Project Logs for C402 V12\PAGE2 FPGA IO&CLK SCH ECO 2017-6-27 22-18-44.LOG | 0 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\Project Logs for C402 V12\PAGE3 FPGA Config&PWR&J SCH ECO 2017-6-27 22-18-44.LOG | 0 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\Project Logs for C402 V12\PAGE4 Connector SCH ECO 2017-6-27 22-18-44.LOG | 0 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\__Previews\C402 V12.PcbDocPreview | 81318 | 2017-06-29
|
| C402 V12硬件原理图及pcb源文件（altium10)\__Previews\PAGE1 BLOCK DIAGRAM.SchDocPreview | 27619 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\__Previews\PAGE2 FPGA IO&CLK.SchDocPreview | 70375 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\__Previews\PAGE3 FPGA Config&PWR&J.SchDocPreview | 78971 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\__Previews\PAGE4 Connector.SchDocPreview | 57279 | 2017-06-19
|
| C402 V12硬件原理图及pcb源文件（altium10)\History | 0 | 2017-06-28
|
| C402 V12硬件原理图及pcb源文件（altium10)\Project Logs for C402 V12 | 0 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10)\__Previews | 0 | 2017-06-27
|
| C402 V12硬件原理图及pcb源文件（altium10) | 0 | 2017-06-28 |
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