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Title: RD1046_lattice Download
 Description: Pulse detection, for general pulse detection, high-speed processing, FPGA dedicated, multi-channel
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FilenameSizeDate
RD1046_lattice\docs\I2C_Bus_specification.pdf 286576  2015-10-20

RD1046_lattice\docs\rd1046.pdf 825330  2015-10-23

RD1046_lattice\docs\rd1046_readme.txt 10870  2015-10-20

RD1046_lattice\project\i2c_master_wb.lpf 208  2015-10-20

RD1046_lattice\project\tst_bench_top_vhd.udo_example 353  2015-10-20

RD1046_lattice\simulation\verilog\rtl_verilog.do 107  2015-10-20

RD1046_lattice\simulation\verilog\run_simulation.bat 27  2015-10-19

RD1046_lattice\simulation\verilog\timing_verilog.do 237  2015-10-20

RD1046_lattice\simulation\verilog\transcript 783  2015-10-20

RD1046_lattice\simulation\vhdl\rtl_vhdl.do 110  2015-10-20

RD1046_lattice\simulation\vhdl\timing_vhdl.do 238  2015-10-20

RD1046_lattice\source\verilog\i2c_master_bit_ctrl.v 19716  2015-10-20

RD1046_lattice\source\verilog\i2c_master_byte_ctrl.v 12992  2015-10-20

RD1046_lattice\source\verilog\i2c_master_defines.v 4330  2015-10-20

RD1046_lattice\source\verilog\i2c_master_registers.v 18055  2015-10-20

RD1046_lattice\source\verilog\i2c_master_wb_top.v 11757  2015-10-20

RD1046_lattice\source\verilog\timescale.v 25  2015-10-20

RD1046_lattice\source\vhdl\i2c_master_bit_ctrl.vhd 19153  2015-10-20

RD1046_lattice\source\vhdl\i2c_master_byte_ctrl.vhd 11389  2015-10-20

RD1046_lattice\source\vhdl\i2c_master_registers.vhd 9381  2015-10-20

RD1046_lattice\source\vhdl\i2c_master_wb_top.vhd 12896  2015-10-20

RD1046_lattice\testbench\mem_init.txt 17  2015-10-20

RD1046_lattice\testbench\verilog\i2c_slave_model.v 13673  2015-10-20

RD1046_lattice\testbench\verilog\timescale.v 25  2015-10-20

RD1046_lattice\testbench\verilog\tst_bench_top.v 17954  2015-10-20

RD1046_lattice\testbench\verilog\wb_master_model.v 7571  2015-10-20

RD1046_lattice\testbench\vhdl\i2c_slave_model.vhd 23421  2015-10-20

RD1046_lattice\testbench\vhdl\tst_bench_top.vhd 19873  2015-10-20

RD1046_lattice\simulation\verilog 0  2015-10-20

RD1046_lattice\simulation\vhdl 0  2015-10-20

RD1046_lattice\source\verilog 0  2015-10-20

RD1046_lattice\source\vhdl 0  2015-10-20

RD1046_lattice\testbench\verilog 0  2015-10-20

RD1046_lattice\testbench\vhdl 0  2015-10-20

RD1046_lattice\docs 0  2015-10-23

RD1046_lattice\pic 0  2015-10-20

RD1046_lattice\project 0  2015-10-20

RD1046_lattice\simulation 0  2015-10-20

RD1046_lattice\source 0  2015-10-20

RD1046_lattice\testbench 0  2015-10-20

RD1046_lattice 0  2015-10-20

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