- Category:
- VHDL-FPGA-Verilog
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- File Size:
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- Update:
- 2018-03-16
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Description: Examine your code to determine if this port should be declared as an INOUT, or if the assignment to this port should not have been made. If this signal connects to submodules, consider the type and lower-level functionality of the port to which it is connected.
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| Filename | Size | Date |
|---|
| Adept SDKv1-3.exe | 175616 | 2010-07-16 |
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