Filename
Size
Date
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01
 0 
 2018-03-15
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 74 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\CODING.md
 5625 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\README.md
 2090 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs
 0 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\.gitignore
 18 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\Doxyfile
 100310 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\Ettus_Logo.png
 4291 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\Makefile
 140 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\fpga.md
 1335 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp1_build_instructions.md
 306 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp2
 0 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp2\build_instructions.md
 1985 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp2\customize_signal_chain.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3
 0 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\build_instructions.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\sim
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\sim\libs_axi.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\sim\libs_general.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\sim\running_testbenches.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\sim\writing_testbenches.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\simulation.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\docs\usrp3\vivado_env_utils.md
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1
 0 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\Makefile.am
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\Makefile.extra
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\TODO
 477 
 2018-03-15
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 0 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\common\fpga_regs_common.v
 3863 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\common\fpga_regs_standard.v
 10233 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\gen_makefile_extra.py
 1865 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\chan_fifo_reader.v
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\channel_demux.v
 1919 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\channel_ram.v
 3284 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\cmd_reader.v
 9547 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\packet_builder.v
 4851 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\register_io.v
 2654 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\rx_buffer_inband.v
 5365 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\tx_buffer_inband.v
 5848 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\tx_packer.v
 2494 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\inband_lib\usb_packet_fifo.v
 3160 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells
 0 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\.gitignore
 4 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\accum32.bsf
 3627 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\accum32.cmp
 1663 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\accum32.inc
 1514 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\accum32.v
 23807 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\accum32_bb.v
 1626 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\accum32_inst.v
 139 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\add32.bsf
 2791 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\add32.cmp
 1607 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\add32.inc
 1502 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\add32.v
 8527 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\add32_bb.v
 1583 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\add32_inst.v
 93 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\addsub16.bsf
 3887 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\addsub16.cmp
 1718 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\addsub16.inc
 1541 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\addsub16.v
 14876 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\addsub16_bb.v
 1687 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\addsub16_inst.v
 193 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\bustri.bsf
 2780 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\bustri.cmp
 1596 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\bustri.inc
 1502 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\bustri.v
 3052 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\bustri_bb.v
 1548 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\bustri_inst.v
 101 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\clk_doubler.v
 9124 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\clk_doubler_bb.v
 7864 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\dspclkpll.v
 11214 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\dspclkpll_bb.v
 1523 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_1kx16.bsf
 3819 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_1kx16.cmp
 1179 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_1kx16.inc
 945 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_1kx16.v
 7125 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_1kx16_bb.v
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 2018-03-15
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 274 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_2k.v
 89879 
 2018-03-15
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_4k.v
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 4187 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\fifo_4kx16_dc.cmp
 1238 
 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 1530 
 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
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 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\sub32.bsf
 3579 
 2018-03-15
fpga-bb2fb07e1ba44d5f43cf0cbf9026bf0fdf3b2c01\usrp1\megacells\sub32.cmp
 1687 
 2018-03-15