- Category:
- Other systems
- Tags:
-
- File Size:
- 28kb
- Update:
- 2018-04-13
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- Uploaded by:
- 小柠
Description: library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity full_adder is
port(
a,b,ci :in std_logic;
s,co :out std_logic);
end entity;
architecture rtl of full_adder is
begin
s<=a xor b xor ci;
co<=(a and b)or(a and ci)or(b and ci);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity adder4_3 is
port(
A,B :in std_logic_vector(3 downto 0);
Ci :in std_logic;
S : out std_logic_vector(3 downto 0);
Co : out std_logic);
end entity;
architecture rtl of adder4_3 is
signal C0,C1,C2,C3,C4:std_logic;
component full_adder is
port(
a,b,ci :in std_logic;
s,co :out std_logic);
end component;
begin
u0:full_adder port map(A(0),B(0),C0,S(0),C1);
u1:full_adder port map(A(1),B(1),C1,S(1),C2);
u2:full_adder port map(A(2),B(2),C2,S(2),C3);
u3:full_adder port map(A(3),B(3),C3,S(3),C4);
end rtl;
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| adder4_3.vhd | 974 | 2018-04-04
|
| 硬件描述语言实验三.doc | 36352 | 2018-03-21
|
| 硬件描述语言实验四.doc | 34816 | 2018-03-27
|
| 硬件描述语言实验五.doc | 35840 | 2018-04-03
|
| adder4.vhd | 673 | 2018-03-21
|
| adder4_2.vhd | 457 | 2018-04-11 |
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