USER Test experiment part program, program design

Title: USER

Category:
VHDL-FPGA-Verilog
Tags:
File Size:
94kb
Update:
2018-04-14
Downloads:
0 Times
Uploaded by:
面朝大海09

Description: Test experiment part program, program design of GSM module.

Downloaders recently: [More information of uploader 面朝大海09]

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File list (Check if you may need any files):

Filename Size Date
USER  0  2013-05-09
USER\JLinkSettings.ini  578  2013-04-06
USER\STM32F10x.s  11307  2013-05-03
USER\test.c  2258  2013-05-08
USER\TEST.hex  189653  2013-05-09
USER\TEST.Opt  4083  2013-05-09
USER\TEST.Uv2  4322  2013-05-04
USER\TEST.uvgui.Administrator  139486  2013-05-09
USER\TEST.uvopt  25908  2013-05-09
USER\TEST.uvproj  21207  2013-05-03

Filename	Size	Date
USER	0	2013-05-09
USER\JLinkSettings.ini	578	2013-04-06
USER\STM32F10x.s	11307	2013-05-03
USER\test.c	2258	2013-05-08
USER\TEST.hex	189653	2013-05-09
USER\TEST.Opt	4083	2013-05-09
USER\TEST.Uv2	4322	2013-05-04
USER\TEST.uvgui.Administrator	139486	2013-05-09
USER\TEST.uvopt	25908	2013-05-09
USER\TEST.uvproj	21207	2013-05-03

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