Description: SPI code written in Verilog, the code is FPGA as the host can send and read data, the upper board verified, when I test the SPI CLK rate is 5M, read and write no problem, stable, as for higher rates have not been tested
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| spi_master.v | 4000 | 2018-03-26 |
Download