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Title: VERILOG Download
 Description: basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.
 Downloaders recently: [More information of uploader sana00]
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File list (Check if you may need any files): 
FilenameSizeDate
VERILOG 0  2019-03-26

VERILOG\ex_3 0  2019-03-26

VERILOG\ex_3\design 0  2019-03-26

VERILOG\ex_3\design\ex_3.v 0  2019-03-26

VERILOG\ex_3\sim 0  2019-03-26

VERILOG\ex1 0  2019-03-24

VERILOG\ex1\design 0  2019-03-24

VERILOG\ex1\design\ex_case.v 0  2019-03-24

VERILOG\ex1\design\ex_cnt.v 607  2019-03-24

VERILOG\ex1\design\ex_cnt.v.bak 601  2019-03-24

VERILOG\ex1\design\ex_wire.v 560  2019-03-24

VERILOG\ex1\design\ex_wire.v.bak 506  2019-03-24

VERILOG\ex1\design\ex1.v 927  2019-03-24

VERILOG\ex1\design\ex1.v.bak 538  2019-03-24

VERILOG\ex1\sim 0  2019-03-24

VERILOG\ex1\sim\ex_cnt.cr.mti 479  2019-03-24

VERILOG\ex1\sim\ex_cnt.mpf 93683  2019-03-24

VERILOG\ex1\sim\tb_ex_cnt.v 891  2019-03-24

VERILOG\ex1\sim\tb_ex_cnt.v.bak 891  2019-03-24

VERILOG\ex1\sim\vsim.wlf 57344  2019-03-24

VERILOG\ex1\sim\work 0  2019-03-24

VERILOG\ex1\sim\work\_info 860  2019-03-24

VERILOG\ex1\sim\work\_lib.qdb 49152  2019-03-24

VERILOG\ex1\sim\work\_lib1_0.qdb 32768  2019-03-24

VERILOG\ex1\sim\work\_lib1_0.qpg 8192  2019-03-24

VERILOG\ex1\sim\work\_lib1_0.qtl 39677  2019-03-24

VERILOG\ex1\sim\work\_vmake 29  2019-03-24

VERILOG\ex2 0  2019-03-25

VERILOG\ex2\design 0  2019-03-25

VERILOG\ex2\design\ex_case.v 1394  2019-03-25

VERILOG\ex2\design\ex_case.v.bak 1378  2019-03-25

VERILOG\ex2\design\ex_case2.v 1945  2019-03-25

VERILOG\ex2\design\ex_case2.v.bak 0  2019-03-25

VERILOG\ex2\quartus_prj 0  2019-03-25

VERILOG\ex2\quartus_prj\新建文本文档.txt 0  2019-03-25

VERILOG\ex2\sim 0  2019-03-25

VERILOG\ex2\sim\ex_case.cr.mti 248  2019-03-25

VERILOG\ex2\sim\ex_case.mpf 93693  2019-03-25

VERILOG\ex2\sim\tb_ex_case.v 1022  2019-03-25

VERILOG\ex2\sim\tb_ex_case.v.bak 970  2019-03-25

VERILOG\ex2\sim\vsim.wlf 57344  2019-03-25

VERILOG\ex2\sim\work 0  2019-03-25

VERILOG\ex2\sim\work\_info 906  2019-03-25

VERILOG\ex2\sim\work\_lib.qdb 49152  2019-03-25

VERILOG\ex2\sim\work\_lib1_0.qdb 32768  2019-03-25

VERILOG\ex2\sim\work\_lib1_0.qpg 24576  2019-03-25

VERILOG\ex2\sim\work\_lib1_0.qtl 35841  2019-03-25

VERILOG\ex2\sim\work\_vmake 29  2019-03-25

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