Description: Verilog prepared by the M-sequence generator, we hope to bring help.
- [fifo the original VHDL code] - In this paper, the source code for Veril
- [VerilogGrammarCheckmanual.Rar] - Verilog Grammar Check manual, it would b
- [ACCUME] - stressed Verilog code-writing norms, is
- [HDLCodingStyle] - Verilog hardware description language pr
- [SPtransform] - Verilog HDL Series and the preparation o
- [fir2] - Verilog prepared by the fir filter can a
- [mstest] - m sequence generator expansion, very goo
- [msa] - Scrambler and Descrambling codec: DVB_S
- [ffcsr] - Pseudo-random sequence generator-filtere
- [m_sequnce] - create m sequence,calculated the crossre
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