Search - maxplus

[Other resource] shifter

Description: 用vhdl实现双向移位寄存器仿真环境MAXPLUS-II，QUARTUS--bidirectional use VHDL simulation environment shift register Segments-II, QUARTUS-
Platform: | Size: 150033 | Author: dm | Hits:

[Other resource] CNT_24

Description: 用vhdl实现24小时计数器，方法简单实用。仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
Platform: | Size: 48512 | Author: dm | Hits:

[Other resource] pulse_change

Description: 用vhdl实现脉冲宽度可控的一简单程序仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
Platform: | Size: 183569 | Author: dm | Hits:

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233299 | Author: 杰轩 | Hits:

[Other resource] MAXPLUGS3

Description: 关于MAXPLUS的学习资料，是初级的教程，包含基本的使用方法，初学者可以参考-Segments of the learning materials is the primary guide contains basic way to use beginners can reference
Platform: | Size: 267644 | Author: 张琪 | Hits:

[Other resource] 脉冲记时CPLD

Description: 工作原理：脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个 74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。开始测试：按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后， LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智能计时器的连续脉冲测试模式中的T30值进行比较。再按下按键即可进行下一次测量。水平有限，见笑。-principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control were overcast. Segments compiler. Test the door to the photoelectric signal an end connected to the mouth of the third J2 pins, for the first pin, should the photoelectric doors to connect (to a total). Testing : press the button, should be able to see the LEDs are lit, instructions to start the rotation inertia set, films such as shading block 30 photoelectric doors, the LED is off, digital possession figures show that for the time value of this unit for seconds Intelligent timer with a continuous pulse mode testing of T30 values were compare
Platform: | Size: 644978 | Author: 高颖峰 | Hits:

[Windows Develop] VHDLgdewrrrrrrrrrrrr

Description: 本设计中选用目前应用较广泛的VHDL硬件电路描述语言，实现对路口交通灯系统的控制器的硬件电路描述，通过编译、仿真，并下载到CPLD器件上进行编程制作，实现交通灯系统的控制过程。EDA技术是用于电子产品设计中比较先进的技术，可以代替设计者完成电子系统设计中的大部分工作，而且可以直接从程序中修改错误及系统功能而不需要硬件电路的支持，既缩短了研发周期，又大大节约了成本，受到了电子工程师的青睐。实现路口交通灯系统的控制方法很多，可以用标准逻辑器件、可编程序控制器PLC、单片机等方案来实现。但是这些控制方法的功能修改及调试都需要硬件电路的支持，在一定程度上增加了功能修改及系统调试的困难。因此，在设计中采用EDA技术，应用目前广泛应用的VHDL硬件电路描述语言，实现交通灯系统控制器的设计，利用MAXPLUSⅡ集成开发环境进行综合、仿真，并下载到CPLD可编程逻辑器件中，完成系统的控制作用。-the current design was chosen over a wide range of VHDL hardware description language circuit. Implementation of traffic lights at the junction of the controller hardware circuit description, compiler, simulation, to download and CPLD programming on production, traffic signal system to achieve the control process. EDA technology is used to design electronic products more advanced technology, designers can replace the complete electronic system design most of the work, but can directly from the process to amend the mistakes and system functions without the need for hardware circuits of support, both to shorten the development cycle, another significant cost savings by the electronic engineers of all ages. Achieving junction traffic signal system control many ways, using standard logic devic
Platform: | Size: 4245 | Author: jazvy | Hits:

[Other resource] taxi1

Description: 出租车计价器，简单、方便，采用verilog hdl语言编写，所用平台是MAXPLUS软件-Taximeter, simple, convenient, using Verilog HDL language, by using the platform of software Segments
Platform: | Size: 977060 | Author: zhz | Hits:

[Other resource] VHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4347 | Author: 单单 | Hits:

[Other resource] RS232-for-vdhl

Description: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Platform: | Size: 162360 | Author: lq | Hits:

[Windows Develop] trafficontrol

Description: 使用verilog编写的交通灯控制程序，各方向通行时间可调，绿灯5s闪烁，在maxplus下调试通过，附仿真波形，在EP系列实验板上测试成功-use Verilog prepared by the traffic lights control procedures, the passage of time adjustable direction, green 5s flickered in maxplus under debugging, simulation waveforms with the EP series of successful experiments board test
Platform: | Size: 113694 | Author: 礼拜 | Hits:

[Other resource] wuzhe

Description: 应用maxplus ii 进行编写工作，主要是进行仿真,很有用-maxplus ii application for the preparation work is primarily for simulation, useful
Platform: | Size: 3376 | Author: 文责 | Hits:

[WEB Code] 040207

Description: 数字钟电路系统由主体电路和扩展电路两大部分组成。其中，主体电路完成数字钟的基本功能，扩展电路完成数字钟的扩展功能。用MAXPLUSⅡ进行电路设计与仿真.-digital clock circuit system from the main circuit and the circuit extended two major components. Among them, the main circuit digital clock to complete the basic functions, expanding digital clock circuit to complete the expansion function. II FPGA used for circuit design and simulation.
Platform: | Size: 455757 | Author: 李明 | Hits:

[source in ebook] dff1

Description: vhdl maxplus d触发器最基本的定义自己看看有没有用-vhdl maxplus d trigger the most basic definition of their own to see if there is no use
Platform: | Size: 24576 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] dotmatrix

Description: MAXplus 2 课程设计点阵的动态显示-A programme of VHDL developed in MAXplus 2 to display one s name in a shifting way.
Platform: | Size: 1024 | Author: 刘进 | Hits:

[VHDL-FPGA-Verilog] MaxPlus

Description: 硬件设计语言-Hardware design language
Platform: | Size: 1032192 | Author: ligong | Hits:

[Other] ALU_Design

Description: 通过maxplus完成的ALU设计，乘法、除法、加减法以及常见的逻辑运算的功能都基本得到实现，其中乘除法使用的是阵列乘除-Completed by maxplus ALU design, multiplication, division, addition and subtraction and common features are the basic logic operations are achieved, which is the array multiplication and division using multiplication and division
Platform: | Size: 433152 | Author: qiren | Hits:

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