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[VHDL-FPGA-Verilog] fir

Description: 真正意思上的fir滤波器课程设计，基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases
Platform: | Size: 1439744 | Author: liyu | Hits:

[VHDL-FPGA-Verilog] poc

Description: The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simulation.
Platform: | Size: 427008 | Author: 程梦飞 | Hits:

[Software Engineering] MAXIIGS

Description: maxplus的说明 讲的很细，不过的话就算是英文的咯-maxplus instructions said very fine, but if even a slightly English
Platform: | Size: 4247552 | Author: deaving | Hits:

[Windows Develop] Maxplus-timing-simulation

Description: 主要介绍Max_plus_的时序仿真与时序分析，对刚入门的很有帮助意义。-Introduced Max_plus_ timing simulation and timing analysis, meaning just getting started helpful.
Platform: | Size: 1224704 | Author: Aaran | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于VHDL硬件描述语言的正弦波利用Maxplus的仿真实例-VHDL hardware description language based on the sine wave using the simulation Maxplus
Platform: | Size: 411648 | Author: dongmei | Hits:

[VHDL-FPGA-Verilog] MAXPLUS_II

Description: maxplus设计电子时钟，电工电子实习专用-maxplus design electronic clock, electrical and electronic practice-specific
Platform: | Size: 290816 | Author: wcg | Hits:

[VHDL-FPGA-Verilog] POC

Description: 用VHDL语言设计一个并行输出控制器POC，作为系统总线个打印机的借口-The purpose of this project is to design and simulate a parallel output controller(poc) which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simulation.
Platform: | Size: 476160 | Author: 张帆帆 | Hits:

[VHDL-FPGA-Verilog] digitalclk

Description: 用maxplus编写的时钟程序。包括天、时、分、秒-make use of language of maxplus to make a clock.include day,hour,minute,second
Platform: | Size: 377856 | Author: 文艺成 | Hits:

[VHDL-FPGA-Verilog] add

Description: 加法计算器，在vhdl下变成完成，包括仿真等。可以完整在quartus，maxplus等下运行-adder vhdl
Platform: | Size: 326656 | Author: 王碧云 | Hits:

[VHDL-FPGA-Verilog] MAXPLUS_Usage

Description: 关于Altera公司MaxPlus II软件的使用方法的快速入门级教程，很适合于准备使用MaxPlus II进行FPGA设计的朋友。-The rapid entry-level tutorial on the use of Altera Corporation the MaxPlus II software, it is suitable for ready to use the MaxPlus II FPGA design friends.
Platform: | Size: 1026048 | Author: 王红卫 | Hits:

[Software Engineering] MAXPPLUS

Description: 通信工程使用的软件maxplus 基本学习电子的都会使用到,这里给大家一点学习内容-The letter project using the software maxplus basic studying electronics are to be used, here to give everyone a little learning content
Platform: | Size: 492544 | Author: forose | Hits:

[VHDL-FPGA-Verilog] vhdl-experiment-guidance

Description: 简单易懂的VHDL实验指导,实验环境MAXPLUS Ⅱ-VHDL experiment guidance
Platform: | Size: 8952832 | Author: 江勇军 | Hits:

[VHDL-FPGA-Verilog] basketball24

Description: 基于FPGA的篮球24秒计时器，开发环境为MAXPLUS-24 second timer in the FPGA-based basketball,Development environment for MAXPLUS
Platform: | Size: 1024 | Author: cynthia | Hits:

[VHDL-FPGA-Verilog] kt1

Description: 基于FPGA的可控100进制可逆计数器，运行环境maxplus-Controlled 100 hex reversible counter FPGA-based operating environment maxplus
Platform: | Size: 263168 | Author: cynthia | Hits:

[Embeded Linux] zreda7

Description: 详细具体的cpu设计maxplus源代码（附图）能完成cpu的基本功能。-Cpu design maxplus detailed and specific source code (with photos) to complete the basic functions of cpu.
Platform: | Size: 552960 | Author: 自然 | Hits:

[VHDL-FPGA-Verilog] yi-wei-er-jin-zhi-quan-jia-qi

Description: 一位二进制全加器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-A binary full source code and detailed documentation WORD, maxplus software running, pin has been configured, EP1K30TC144-3
Platform: | Size: 133120 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] shu-kong-fen-pin-qi

Description: 数控分频器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-NC divider source code and detailed documentation WORD, maxplus software running, pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 167936 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] jia-fa-ji-shu-qi

Description: 含异步清零和同步使能的加法计数器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-Asynchronous and synchronous cleared with the addition of the counter enable source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 37888 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] XU-LIE-JIAN-CE-QI

Description: 用状态机实现序列检测器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 41984 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] cai-yang-dian-lu-shi-xian-ADC0809

Description: 用状态机对ADC0809的采样控制电路的实现的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State machine to achieve ADC0809 sampling control circuit of the source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 41984 | Author: 邱海涛 | Hits:
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