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Description: RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
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Size: 2048 |
Author: dinsh |
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Description: RS232串行通信,采用VHDL编程,由波特率发生器,接收器和发送器构成-RS232 serial communication using VHDL programming, by the baud rate generator, receiver and transmitter constitute
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Size: 1024 |
Author: 幸运 |
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Description: Controller RS232 in VHDL
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Size: 2048 |
Author: darek |
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Description: RS232 Transmitter VHDL Code
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Size: 1024 |
Author: mohd |
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Description: Rs232 Receiver VHDL code
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Size: 1024 |
Author: mohd |
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Description: 数码管显示,温度传感,红外感应,流水灯蜂鸣器,PS2,RS232的相关VHDL程序,已经在MAX-IIEPM570开发板上测试成功-Digital display, temperature sensor, infrared sensor, water lights buzzer, PS2, RS232 relevant VHDL procedures have been developed at MAX-IIEPM570 the success of on-board test
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Size: 9216 |
Author: 刘运学 |
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Description: Working RS232 controller running at 9600 Hz.
Consist of Transmitter and Receiver Module.
Tested in FPGA Spartan 3
Included files for testing at FPGA
- Scan4digit .vhd - to display at 7 sgement display
- D4to7 .vhd - Convert HEX decimal to ASCII code.
-Working RS232 controller running at 9600 Hz.
Consist of Transmitter and Receiver Module.
Tested in FPGA Spartan 3
Included files for testing at FPGA
- Scan4digit .vhd- to display at 7 sgement display
- D4to7 .vhd- Convert HEX decimal to ASCII code.
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Size: 5120 |
Author: Ikki |
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Description: controller RS232 for receiving serial data at different speeds
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Size: 1024 |
Author: Natacho |
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Description: This project is a RS232 Controller used to communicate two devices.
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Size: 505856 |
Author: Arley |
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Description: This module use OV7620 digital camera on the 24-bit RBG (8:8:8) data and display that in RS232 uart interface
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Size: 5120 |
Author: Joelmir J Lopes |
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Description: fpga的串口读写程序,经硬件测试成功,波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
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Size: 384000 |
Author: cjy |
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Description: 该程序为RS232串口通信的VERILOG程序,在FPGA上已通过验证,在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
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Size: 1024 |
Author: su |
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Description: VHDL写的RS232和RS485通信代码,很基础的一个工具-VHDL written RS232 and RS485 communication code, it is a tool based on
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Size: 583680 |
Author: dvp |
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Description: FPGA应用,Altera的FPGA开发板原理图汇集,FPGA最小系统,rs232串口转换,VGA显示-FPGA applications, Altera' s FPGA development board schematic pooling, FPGA minimum system, rs232 serial converter, VGA display etc.
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Size: 1720320 |
Author: 吴贵锋 |
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Description: 通过FPGA实现串口通信,结果在超级终端可见-Serial communication through the FPGA, the result can be seen in the HyperTerminal
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Size: 641024 |
Author: chengliu |
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Description: Example of a screen shot module in a FPGA (upload bitmap file by RS232)
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Size: 2048 |
Author: Charles |
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Description: 串口通讯 rs232 verilog程序,一次接受传送8bits-rs232 verilog project,reciver or trancimiter 8 bits onece
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Size: 2048 |
Author: 王翰林 |
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Description: RS232设计,硬件测试通过,VERILOG实现的,比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
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Size: 1249280 |
Author: 洪依 |
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Description: rs232 interface for xilinx spartan 3e
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Size: 8192 |
Author: MILIND |
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Description: A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
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Size: 45056 |
Author: sandeep |
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