Description: QQ again and again to see the plug, to achieve the automatic elimination of the function and the function of a key spike and the function of the automatic start. Platform: |
Size: 1914880 |
Author:liutao |
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Description: Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed Platform: |
Size: 4391936 |
Author:王远震 |
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Description: Quartus HDLC codec under development include design documentation and reports, by RTL and timing simulation Platform: |
Size: 6890496 |
Author:王远震 |
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Description: sprintn formats a number n in base b and puts output to callers buffer. We don t use recursion to avoid deep kernel stacks. Platform: |
Size: 2048 |
Author:xoubqmou |
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