The project s main function is to achieve by the VHDL language multifunction digital electronic clock

digital_clk
...........\2.txt
...........\cmp_state.ini
...........\db
...........\..\add_sub_03c.tdf
...........\..\add_sub_13c.tdf
...........\..\add_sub_19b.tdf
...........\..\add_sub_23c.tdf
...........\..\add_sub_och.tdf
...........\..\add_sub_pch.tdf
...........\..\add_sub_u2c.tdf
...........\..\add_sub_v2c.tdf
...........\..\digital_clk.asm.qmsg
...........\..\digital_clk.cmp.cdb
...........\..\digital_clk.cmp.ddb
...........\..\digital_clk.cmp.hdb
...........\..\digital_clk.cmp.rdb
...........\..\digital_clk.cmp.tdb
...........\..\digital_clk.csf.qmsg
...........\..\digital_clk.db_info
...........\..\digital_clk.digital_clk.sld_design_entry.sci
...........\..\digital_clk.fit.qmsg
...........\..\digital_clk.hif
...........\..\digital_clk.map.cdb
...........\..\digital_clk.map.hdb
...........\..\digital_clk.map.qmsg
...........\..\digital_clk.pre_map.hdb
...........\..\digital_clk.project.hdb
...........\..\digital_clk.rtlv.hdb
...........\..\digital_clk.rtlv_sg.cdb
...........\..\digital_clk.rtlv_sg_swap.cdb
...........\..\digital_clk.sgdiff.cdb
...........\..\digital_clk.sgdiff.hdb
...........\..\digital_clk.tan.qmsg
...........\..\digital_clk_cmp.qrpt
...........\..\digital_clk_hier_info
...........\..\digital_clk_syn_hier_info
...........\digital_clk.asm.rpt
...........\digital_clk.cdf
...........\digital_clk.done
...........\digital_clk.fit.eqn
...........\digital_clk.fit.rpt
...........\digital_clk.flow.rpt
...........\digital_clk.map.eqn
...........\digital_clk.map.rpt
...........\digital_clk.pin
...........\digital_clk.pof
...........\digital_clk.qpf
...........\digital_clk.qsf
...........\digital_clk.qws
...........\digital_clk.sof
...........\digital_clk.tan.rpt
...........\digital_clk.tan.summary
...........\digital_clk.txt
...........\digital_clk.vhd
...........\ok.txt

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