[VHDL-FPGA-Verilog] Anvyl LED Runner

Description: This code runs the leds on the Anvyl development board Spartan 6
Platform: | Size: 1620 | Author: umarshahbaz@gmail.com | Hits:

[VHDL-FPGA-Verilog] arm_vhdl-master

Description: Fully functional ARM processor with CoreSight debugging subsystem developed by ARM
Platform: | Size: 906464 | Author: juenkko | Hits:

[VHDL-FPGA-Verilog] xapp_hls_Matrix Multiply

Description: This repository includes a pure Vitis HLS implementation of matrix-matrix multiplication (A*B=C) for Xilinx FPGAs, using Xilinx Vitis to instantiate memory and PCIe controllers and interface with the host. Experiments ru
Platform: | Size: 585044 | Author: 1679556379@qq.com | Hits:

[VHDL-FPGA-Verilog] adc test

Description: This is a zynq 7020 fpga adc test.
Platform: | Size: 4476 | Author: ravisaini | Hits:

[VHDL-FPGA-Verilog] adc

Description: fpga adc test program.
Platform: | Size: 5336 | Author: ravisaini | Hits:

[VHDL-FPGA-Verilog] uart-vhdl

Description: Code to receive information with VHDL
Platform: | Size: 1108036 | Author: dornabit | Hits:

[VHDL-FPGA-Verilog] Divider-vhdl

Description: Divider-VHDL by spartan 6
Platform: | Size: 16131 | Author: dornabit | Hits:

[VHDL-FPGA-Verilog] fifo-vhdl

Description: code fifo by spartan6
Platform: | Size: 14513 | Author: dornabit | Hits:

[VHDL-FPGA-Verilog] sum in vhdl

Description: Sum module for Cyclone IV
Platform: | Size: 786390 | Author: w3bpunk | Hits:

[VHDL-FPGA-Verilog] Adder of three numbers VHDL

Description: Adder of three numbers module in vhdl
Platform: | Size: 794401 | Author: w3bpunk | Hits:

[VHDL-FPGA-Verilog] Counter up and down

Description: vhdl code + testbench of up and down counter based on t-trigger
Platform: | Size: 34975 | Author: w3bpunk | Hits:

[VHDL-FPGA-Verilog] decoder

Description: 4 bit input decoder binary to binary-decimal with testbench files
Platform: | Size: 660448 | Author: w3bpunk | Hits: