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VHDL-FPGA-Verilog list
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spi master and slaver code
Update : 2020-08-27 Size : 7.98kb Publisher : sandayyang

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The verification environment based on UVM platform aims at router module of router, which can be used for reference
Update : 2020-09-02 Size : 30kb Publisher : 迪哥

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xilinx async_comm data recovery
Update : 2020-09-09 Size : 12.42kb Publisher : 104758548@qq.com

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10GE Ethernet FPGA VHDL verilog
Update : 2020-09-09 Size : 595.92kb Publisher : 104758548@qq.com

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The AM modulation and demodulation code based on artix-7 FPGA, after reading the signal from AD, carries out AM modulation, and demodulates the output (the code is divided into two projects, namely AM modulation and demo
Update : 2024-12-21 Size : 39.13mb Publisher : Emmanuel000

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SRAM verilog fpga vivado ise quartus.
Update : 2024-12-21 Size : 1kb Publisher : hwz

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Sampling ad9481 with FPGA
Update : 2024-12-21 Size : 32kb Publisher : 山粉小圆子

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Xilinx 7 Series FPGA multiboot function description document to increase FPGA loading reliability
Update : 2024-12-21 Size : 425kb Publisher : superlizechao

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ethernet verilog coding,please read it and download it
Update : 2024-12-21 Size : 5kb Publisher : TONYSSSS

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AMBA AHB 2.0 VIP in SystemVerilog UVM
Update : 2024-12-21 Size : 31kb Publisher : wangliu433

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AMBA AHB 2.0 VIP in SystemVerilog UVM
Update : 2024-12-21 Size : 1kb Publisher : wangliu433

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Synchronization technology of digital communication MATLAB FPGA Altera Verilog.pdf
Update : 2020-11-02 Size : 49.67mb Publisher : 小博小超人
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