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S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the l
Update : 2022-05-01 Size : 1.06mb Publisher : xptogudovan

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Flexpret is RISCv implementation core hardware multithreaded
Update : 2022-05-01 Size : 1.7mb Publisher : xptogudovan

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complete jpeg ls, jpeg2000 document code, by system verilog
Update : 2022-06-14 Size : 3.17mb Publisher : kelvin_user

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h264 video decoder h264 video decoder
Update : 2022-07-23 Size : 12.09mb Publisher : perst@sadsa.com

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Altera's Quartus II 6.0 Handbook
Update : 2022-08-30 Size : 25.51mb Publisher : alz4062

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Altera's Quartus II 7.1 Handbook
Update : 2022-08-30 Size : 22.93mb Publisher : alz4062

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Altera's Quartus II 7.2 Handbook
Update : 2022-08-30 Size : 23.06mb Publisher : alz4062

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Altera's Quartus II 8.0 Handbook
Update : 2022-08-30 Size : 24.49mb Publisher : alz4062

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Altera's Quartus II 8.1 Handbook
Update : 2022-08-30 Size : 22.22mb Publisher : alz4062

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Altera Quartus 13.1 Handbook
Update : 2022-08-31 Size : 22.97mb Publisher : alz4062

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this driver takes a 24 bit RGB stream and converts into a format for the ECX334c assuming a SERDES on the output.
Update : 2022-09-13 Size : 1.04kb Publisher : gswdh_

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PAL GAL design using vhdl used in gamika pc
Update : 2022-09-13 Size : 1.54kb Publisher : essaidioualid@gmail.com
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