One is to use Verilog procedures also can be used

Verilog_VGA
...........\db
...........\..\VGA.asm.qmsg
...........\..\VGA.asm_labs.ddb
...........\..\VGA.cbx.xml
...........\..\VGA.cmp.cdb
...........\..\VGA.cmp.hdb
...........\..\VGA.cmp.qrpt
...........\..\VGA.cmp.rdb
...........\..\VGA.cmp.tdb
...........\..\VGA.cmp0.ddb
...........\..\VGA.dbp
...........\..\VGA.db_info
...........\..\VGA.eco.cdb
...........\..\VGA.fit.qmsg
...........\..\VGA.hier_info
...........\..\VGA.hif
...........\..\VGA.map.cdb
...........\..\VGA.map.hdb
...........\..\VGA.map.qmsg
...........\..\VGA.pre_map.cdb
...........\..\VGA.pre_map.hdb
...........\..\VGA.psp
...........\..\VGA.rtlv.hdb
...........\..\VGA.rtlv_sg.cdb
...........\..\VGA.rtlv_sg_swap.cdb
...........\..\VGA.sgdiff.cdb
...........\..\VGA.sgdiff.hdb
...........\..\VGA.signalprobe.cdb
...........\..\VGA.sld_design_entry.sci
...........\..\VGA.sld_design_entry_dsc.sci
...........\..\VGA.syn_hier_info
...........\..\VGA.tan.qmsg
...........\setup.tcl
...........\VGA.asm.rpt
...........\VGA.bdf
...........\VGA.cdf
...........\VGA.done
...........\VGA.fit.eqn
...........\VGA.fit.rpt
...........\VGA.fit.summary
...........\VGA.flow.rpt
...........\VGA.map.eqn
...........\VGA.map.rpt
...........\VGA.map.summary
...........\VGA.pin
...........\VGA.pof
...........\VGA.qpf
...........\VGA.qsf
...........\VGA.qws
...........\VGA.sof
...........\VGA.tan.rpt
...........\VGA.tan.summary
...........\VGAsignal.bsf
...........\VGAsignal.v
...........\VGA_assignment_defaults.qdf

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